Geetha Sowjanya f935448acf iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126 ... Cavium ThunderX2 SMMU doesn't support MSI and also doesn't have unique irq lines for gerror, eventq and cmdq-sync. New named irq "combined" is set as a errata workaround, which allows to share the irq line by register single irq handler for all the interrupts. Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Geetha sowjanya <gakula@caviumnetworks.com> [will: reworked irq equality checking and added SPI check] Signed-off-by: Will Deacon <will.deacon@arm.com>		2017-06-23 17:58:04 +01:00
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arm,smmu-v3.txt	iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #126	2017-06-23 17:58:04 +01:00
arm,smmu.txt	iommu/arm-smmu: Add global SMR masking property	2017-04-06 16:06:43 +01:00
iommu.txt
mediatek,iommu.txt	dt-bindings: mediatek: add descriptions for mediatek mt2701 iommu and smi	2016-06-21 11:36:19 +02:00
msm,iommu-v0.txt	documentation: iommu: Add bindings for msm,iommu-v0 ip	2016-06-21 13:56:00 +02:00
nvidia,tegra20-gart.txt
nvidia,tegra30-smmu.txt
renesas,ipmmu-vmsa.txt	iommu/ipmmu-vmsa: Add r8a7795 DT binding	2016-03-03 10:59:17 +01:00
rockchip,iommu.txt
samsung,sysmmu.txt	iommu/exynos: Add support for v5 SYSMMU	2016-02-25 15:32:10 +01:00
ti,omap-iommu.txt	Documentation: dt: Update OMAP iommu bindings for DRA7 DSPs	2015-10-14 14:35:47 +02:00