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f9040550be
linux/arch/arm/mach-tegra
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Russell King f9040550be ARM: l2c: tegra: remove cache size override 
The cache size should already be present in the L2 cache auxiliary
control register: it is part of the integration process to configure
the hardware IP.  Most platforms get this right, yet still many
cargo-cult program, and assume that they always need specifying to
the L2 cache code.  Remove them so we can find out which really need
this.

Acked-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2014-05-30 00:50:10 +01:00
..
apbio.c tree-wide: use reinit_completion instead of INIT_COMPLETION 2013-11-15 09:32:21 +09:00
apbio.h
board-paz00.c ARM: tegra: add gpiod_lookup table for paz00 2013-12-11 12:49:29 +01:00
board.h ARM: tegra: delete stale header content 2013-09-17 13:44:21 -06:00
common.h Revert "ARM: tegra: add cpu_disable for hotplug" 2013-07-19 10:00:37 -06:00
cpuidle-tegra20.c ARM: tegra: disable LP2 cpuidle state if PCIe is enabled 2013-08-13 12:07:56 -06:00
cpuidle-tegra30.c ARM: tegra: don't pass CPU ID to tegra_{set,clear}_cpu_in_lp2 2013-06-05 11:44:58 -06:00
cpuidle-tegra114.c ARM: tegra: cpuidle: use firmware for power down 2014-02-18 13:46:50 -07:00
cpuidle.c ARM: tegra: enable CPU idle for Tegra124 2013-10-18 16:28:09 -06:00
cpuidle.h ARM: tegra: disable LP2 cpuidle state if PCIe is enabled 2013-08-13 12:07:56 -06:00
flowctrl.c ARM: tegra: add LP1 support code for Tegra124 2013-10-18 16:28:10 -06:00
flowctrl.h ARM: tegra: shut off the CPU rail when the last CPU in suspend 2013-07-19 10:08:07 -06:00
fuse.c ARM: tegra: SoC-specific core code changes 2013-12-26 11:02:25 -08:00
fuse.h ARM: tegra: add Tegra124 SoC support 2013-10-18 16:28:07 -06:00
headsmp.S ARM: tegra: do v7_invalidate_l1 only when CPU is Cortex-A9 2013-07-19 10:08:04 -06:00
hotplug.c ARM: tegra: CPU hotplug support for Tegra124 2013-10-18 16:28:08 -06:00
io.c
iomap.h ARM: tegra: use section-sized static mappings for LPAE too 2013-12-04 12:25:25 -07:00
irammap.h ARM: tegra: move resume vector define to irammap.h 2013-09-17 13:44:22 -06:00
irq.c ARM: tegra114: Reprogram GIC CPU interface to bypass IRQ on CPU PM entry 2013-07-19 10:07:14 -06:00
irq.h ARM: tegra: irq: add wake up handling 2013-04-03 14:31:32 -06:00
Kconfig ARM: tegra: remove TEGRA_EMC_SCALING_ENABLE 2014-04-24 15:29:12 +02:00
Makefile ARM: tegra: remove tegra EMC scaling driver 2014-02-25 10:58:06 -07:00
platsmp.c ARM: tegra: don't timeout if CPU is powergated 2014-02-12 12:10:58 -07:00
pm-tegra20.c ARM: tegra: add LP1 suspend support for Tegra20 2013-08-12 13:30:11 -06:00
pm-tegra30.c ARM: tegra: add LP1 suspend support for Tegra30 2013-08-12 13:30:11 -06:00
pm.c arm, pm, vmpressure: add missing slab.h includes 2014-02-03 13:24:01 -05:00
pm.h ARM: tegra: delete stale header content 2013-09-17 13:44:21 -06:00
pmc.c ARM: tegra: Remove duplicate powergate defines 2013-10-18 16:28:10 -06:00
pmc.h ARM: tegra: remove common.c 2013-09-17 13:44:21 -06:00
powergate.c ARM: tegra: Export I/O rail functions 2014-02-25 13:16:32 -07:00
reset-handler.S ARM: tegra: make tegra_resume can work with current and later chips 2013-10-18 16:28:08 -06:00
reset.c ARM: tegra: set CPU reset handler using firmware 2013-12-13 12:50:31 -07:00
reset.h ARM: tegra: add common LP1 suspend support 2013-08-12 13:29:24 -06:00
sleep-tegra20.S ARM: tegra: move resume vector define to irammap.h 2013-09-17 13:44:22 -06:00
sleep-tegra30.S ARM: tegra: add LP1 support code for Tegra124 2013-10-18 16:28:10 -06:00
sleep.h ARM: l2c: fix register naming 2014-05-30 00:48:43 +01:00
sleep.S ARM: tegra: add LP1 suspend support for Tegra30 2013-08-12 13:30:11 -06:00
tegra20_speedo.c
tegra30_speedo.c
tegra114_speedo.c ARM: tegra: add speedo-based process id for Tegra114 2013-03-19 11:52:06 -06:00
tegra.c ARM: l2c: tegra: remove cache size override 2014-05-30 00:50:10 +01:00