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029c936ae7
Export PLL operations and register functions for different type of clock driver used. Co-developed-by: Edward-JW Yang <edward-jw.yang@mediatek.com> Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.com> Signed-off-by: Johnson Wang <johnson.wang@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20221121122957.21611-2-johnson.wang@mediatek.com Signed-off-by: Chen-Yu Tsai <wenst@chromium.org>
113 lines
2.9 KiB
C
113 lines
2.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2014 MediaTek Inc.
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* Author: James Liao <jamesjj.liao@mediatek.com>
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*/
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#ifndef __DRV_CLK_MTK_PLL_H
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#define __DRV_CLK_MTK_PLL_H
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#include <linux/clk-provider.h>
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#include <linux/types.h>
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struct clk_ops;
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struct clk_hw_onecell_data;
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struct device_node;
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struct mtk_pll_div_table {
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u32 div;
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unsigned long freq;
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};
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#define HAVE_RST_BAR BIT(0)
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#define PLL_AO BIT(1)
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#define POSTDIV_MASK GENMASK(2, 0)
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struct mtk_pll_data {
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int id;
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const char *name;
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u32 reg;
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u32 pwr_reg;
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u32 en_mask;
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u32 pd_reg;
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u32 tuner_reg;
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u32 tuner_en_reg;
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u8 tuner_en_bit;
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int pd_shift;
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unsigned int flags;
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const struct clk_ops *ops;
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u32 rst_bar_mask;
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unsigned long fmin;
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unsigned long fmax;
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int pcwbits;
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int pcwibits;
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u32 pcw_reg;
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int pcw_shift;
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u32 pcw_chg_reg;
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const struct mtk_pll_div_table *div_table;
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const char *parent_name;
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u32 en_reg;
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u8 pll_en_bit; /* Assume 0, indicates BIT(0) by default */
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};
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/*
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* MediaTek PLLs are configured through their pcw value. The pcw value describes
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* a divider in the PLL feedback loop which consists of 7 bits for the integer
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* part and the remaining bits (if present) for the fractional part. Also they
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* have a 3 bit power-of-two post divider.
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*/
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struct mtk_clk_pll {
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struct clk_hw hw;
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void __iomem *base_addr;
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void __iomem *pd_addr;
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void __iomem *pwr_addr;
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void __iomem *tuner_addr;
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void __iomem *tuner_en_addr;
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void __iomem *pcw_addr;
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void __iomem *pcw_chg_addr;
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void __iomem *en_addr;
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const struct mtk_pll_data *data;
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};
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int mtk_clk_register_plls(struct device_node *node,
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const struct mtk_pll_data *plls, int num_plls,
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struct clk_hw_onecell_data *clk_data);
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void mtk_clk_unregister_plls(const struct mtk_pll_data *plls, int num_plls,
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struct clk_hw_onecell_data *clk_data);
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extern const struct clk_ops mtk_pll_ops;
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static inline struct mtk_clk_pll *to_mtk_clk_pll(struct clk_hw *hw)
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{
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return container_of(hw, struct mtk_clk_pll, hw);
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}
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int mtk_pll_is_prepared(struct clk_hw *hw);
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int mtk_pll_prepare(struct clk_hw *hw);
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void mtk_pll_unprepare(struct clk_hw *hw);
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unsigned long mtk_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate);
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void mtk_pll_calc_values(struct mtk_clk_pll *pll, u32 *pcw, u32 *postdiv,
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u32 freq, u32 fin);
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int mtk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate);
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long mtk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long *prate);
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struct clk_hw *mtk_clk_register_pll_ops(struct mtk_clk_pll *pll,
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const struct mtk_pll_data *data,
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void __iomem *base,
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const struct clk_ops *pll_ops);
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struct clk_hw *mtk_clk_register_pll(const struct mtk_pll_data *data,
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void __iomem *base);
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void mtk_clk_unregister_pll(struct clk_hw *hw);
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__iomem void *mtk_clk_pll_get_base(struct clk_hw *hw,
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const struct mtk_pll_data *data);
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#endif /* __DRV_CLK_MTK_PLL_H */
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