Heiko Stuebner a35707c3d8 riscv: add memory-type errata for T-Head ... Some current cpus based on T-Head cores implement memory-types way different than described in the svpbmt spec even going so far as using PTE bits marked as reserved. Add the T-Head vendor-id and necessary errata code to replace the affected instructions. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Tested-by: Samuel Holland <samuel@sholland.org> Link: https://lore.kernel.org/r/20220511192921.2223629-13-heiko@sntech.de Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>		2022-05-11 21:36:33 -07:00
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sifive	riscv: add memory-type errata for T-Head	2022-05-11 21:36:33 -07:00
thead	riscv: add memory-type errata for T-Head	2022-05-11 21:36:33 -07:00
Makefile	riscv: add memory-type errata for T-Head	2022-05-11 21:36:33 -07:00