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4701643425
It was a mistake to mark the PL031 IRQ as shared (for the U8500), we misread the datasheet. Get rid of this. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Cc: Jonas Aberg <jonas.aberg@stericsson.com> Cc: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com> Acked-by: Alessandro Zummo <a.zummo@towertech.it> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
503 lines
13 KiB
C
503 lines
13 KiB
C
/*
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* drivers/rtc/rtc-pl031.c
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*
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* Real Time Clock interface for ARM AMBA PrimeCell 031 RTC
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*
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* Author: Deepak Saxena <dsaxena@plexity.net>
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*
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* Copyright 2006 (c) MontaVista Software, Inc.
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*
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* Author: Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
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* Copyright 2010 (c) ST-Ericsson AB
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/module.h>
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#include <linux/rtc.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/amba/bus.h>
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#include <linux/io.h>
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#include <linux/bcd.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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/*
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* Register definitions
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*/
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#define RTC_DR 0x00 /* Data read register */
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#define RTC_MR 0x04 /* Match register */
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#define RTC_LR 0x08 /* Data load register */
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#define RTC_CR 0x0c /* Control register */
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#define RTC_IMSC 0x10 /* Interrupt mask and set register */
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#define RTC_RIS 0x14 /* Raw interrupt status register */
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#define RTC_MIS 0x18 /* Masked interrupt status register */
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#define RTC_ICR 0x1c /* Interrupt clear register */
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/* ST variants have additional timer functionality */
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#define RTC_TDR 0x20 /* Timer data read register */
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#define RTC_TLR 0x24 /* Timer data load register */
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#define RTC_TCR 0x28 /* Timer control register */
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#define RTC_YDR 0x30 /* Year data read register */
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#define RTC_YMR 0x34 /* Year match register */
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#define RTC_YLR 0x38 /* Year data load register */
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#define RTC_CR_CWEN (1 << 26) /* Clockwatch enable bit */
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#define RTC_TCR_EN (1 << 1) /* Periodic timer enable bit */
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/* Common bit definitions for Interrupt status and control registers */
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#define RTC_BIT_AI (1 << 0) /* Alarm interrupt bit */
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#define RTC_BIT_PI (1 << 1) /* Periodic interrupt bit. ST variants only. */
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/* Common bit definations for ST v2 for reading/writing time */
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#define RTC_SEC_SHIFT 0
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#define RTC_SEC_MASK (0x3F << RTC_SEC_SHIFT) /* Second [0-59] */
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#define RTC_MIN_SHIFT 6
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#define RTC_MIN_MASK (0x3F << RTC_MIN_SHIFT) /* Minute [0-59] */
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#define RTC_HOUR_SHIFT 12
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#define RTC_HOUR_MASK (0x1F << RTC_HOUR_SHIFT) /* Hour [0-23] */
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#define RTC_WDAY_SHIFT 17
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#define RTC_WDAY_MASK (0x7 << RTC_WDAY_SHIFT) /* Day of Week [1-7] 1=Sunday */
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#define RTC_MDAY_SHIFT 20
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#define RTC_MDAY_MASK (0x1F << RTC_MDAY_SHIFT) /* Day of Month [1-31] */
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#define RTC_MON_SHIFT 25
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#define RTC_MON_MASK (0xF << RTC_MON_SHIFT) /* Month [1-12] 1=January */
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#define RTC_TIMER_FREQ 32768
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struct pl031_local {
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struct rtc_device *rtc;
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void __iomem *base;
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u8 hw_designer;
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u8 hw_revision:4;
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};
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static int pl031_alarm_irq_enable(struct device *dev,
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unsigned int enabled)
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{
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struct pl031_local *ldata = dev_get_drvdata(dev);
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unsigned long imsc;
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/* Clear any pending alarm interrupts. */
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writel(RTC_BIT_AI, ldata->base + RTC_ICR);
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imsc = readl(ldata->base + RTC_IMSC);
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if (enabled == 1)
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writel(imsc | RTC_BIT_AI, ldata->base + RTC_IMSC);
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else
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writel(imsc & ~RTC_BIT_AI, ldata->base + RTC_IMSC);
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return 0;
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}
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/*
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* Convert Gregorian date to ST v2 RTC format.
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*/
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static int pl031_stv2_tm_to_time(struct device *dev,
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struct rtc_time *tm, unsigned long *st_time,
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unsigned long *bcd_year)
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{
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int year = tm->tm_year + 1900;
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int wday = tm->tm_wday;
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/* wday masking is not working in hardware so wday must be valid */
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if (wday < -1 || wday > 6) {
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dev_err(dev, "invalid wday value %d\n", tm->tm_wday);
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return -EINVAL;
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} else if (wday == -1) {
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/* wday is not provided, calculate it here */
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unsigned long time;
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struct rtc_time calc_tm;
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rtc_tm_to_time(tm, &time);
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rtc_time_to_tm(time, &calc_tm);
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wday = calc_tm.tm_wday;
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}
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*bcd_year = (bin2bcd(year % 100) | bin2bcd(year / 100) << 8);
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*st_time = ((tm->tm_mon + 1) << RTC_MON_SHIFT)
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| (tm->tm_mday << RTC_MDAY_SHIFT)
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| ((wday + 1) << RTC_WDAY_SHIFT)
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| (tm->tm_hour << RTC_HOUR_SHIFT)
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| (tm->tm_min << RTC_MIN_SHIFT)
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| (tm->tm_sec << RTC_SEC_SHIFT);
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return 0;
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}
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/*
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* Convert ST v2 RTC format to Gregorian date.
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*/
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static int pl031_stv2_time_to_tm(unsigned long st_time, unsigned long bcd_year,
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struct rtc_time *tm)
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{
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tm->tm_year = bcd2bin(bcd_year) + (bcd2bin(bcd_year >> 8) * 100);
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tm->tm_mon = ((st_time & RTC_MON_MASK) >> RTC_MON_SHIFT) - 1;
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tm->tm_mday = ((st_time & RTC_MDAY_MASK) >> RTC_MDAY_SHIFT);
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tm->tm_wday = ((st_time & RTC_WDAY_MASK) >> RTC_WDAY_SHIFT) - 1;
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tm->tm_hour = ((st_time & RTC_HOUR_MASK) >> RTC_HOUR_SHIFT);
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tm->tm_min = ((st_time & RTC_MIN_MASK) >> RTC_MIN_SHIFT);
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tm->tm_sec = ((st_time & RTC_SEC_MASK) >> RTC_SEC_SHIFT);
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tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
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tm->tm_year -= 1900;
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return 0;
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}
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static int pl031_stv2_read_time(struct device *dev, struct rtc_time *tm)
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{
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struct pl031_local *ldata = dev_get_drvdata(dev);
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pl031_stv2_time_to_tm(readl(ldata->base + RTC_DR),
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readl(ldata->base + RTC_YDR), tm);
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return 0;
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}
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static int pl031_stv2_set_time(struct device *dev, struct rtc_time *tm)
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{
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unsigned long time;
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unsigned long bcd_year;
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struct pl031_local *ldata = dev_get_drvdata(dev);
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int ret;
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ret = pl031_stv2_tm_to_time(dev, tm, &time, &bcd_year);
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if (ret == 0) {
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writel(bcd_year, ldata->base + RTC_YLR);
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writel(time, ldata->base + RTC_LR);
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}
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return ret;
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}
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static int pl031_stv2_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
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{
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struct pl031_local *ldata = dev_get_drvdata(dev);
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int ret;
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ret = pl031_stv2_time_to_tm(readl(ldata->base + RTC_MR),
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readl(ldata->base + RTC_YMR), &alarm->time);
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alarm->pending = readl(ldata->base + RTC_RIS) & RTC_BIT_AI;
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alarm->enabled = readl(ldata->base + RTC_IMSC) & RTC_BIT_AI;
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return ret;
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}
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static int pl031_stv2_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
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{
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struct pl031_local *ldata = dev_get_drvdata(dev);
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unsigned long time;
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unsigned long bcd_year;
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int ret;
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/* At the moment, we can only deal with non-wildcarded alarm times. */
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ret = rtc_valid_tm(&alarm->time);
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if (ret == 0) {
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ret = pl031_stv2_tm_to_time(dev, &alarm->time,
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&time, &bcd_year);
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if (ret == 0) {
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writel(bcd_year, ldata->base + RTC_YMR);
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writel(time, ldata->base + RTC_MR);
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pl031_alarm_irq_enable(dev, alarm->enabled);
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}
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}
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return ret;
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}
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static irqreturn_t pl031_interrupt(int irq, void *dev_id)
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{
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struct pl031_local *ldata = dev_id;
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unsigned long rtcmis;
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unsigned long events = 0;
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rtcmis = readl(ldata->base + RTC_MIS);
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if (rtcmis) {
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writel(rtcmis, ldata->base + RTC_ICR);
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if (rtcmis & RTC_BIT_AI)
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events |= (RTC_AF | RTC_IRQF);
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/* Timer interrupt is only available in ST variants */
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if ((rtcmis & RTC_BIT_PI) &&
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(ldata->hw_designer == AMBA_VENDOR_ST))
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events |= (RTC_PF | RTC_IRQF);
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rtc_update_irq(ldata->rtc, 1, events);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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static int pl031_read_time(struct device *dev, struct rtc_time *tm)
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{
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struct pl031_local *ldata = dev_get_drvdata(dev);
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rtc_time_to_tm(readl(ldata->base + RTC_DR), tm);
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return 0;
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}
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static int pl031_set_time(struct device *dev, struct rtc_time *tm)
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{
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unsigned long time;
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struct pl031_local *ldata = dev_get_drvdata(dev);
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int ret;
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ret = rtc_tm_to_time(tm, &time);
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if (ret == 0)
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writel(time, ldata->base + RTC_LR);
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return ret;
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}
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static int pl031_read_alarm(struct device *dev, struct rtc_wkalrm *alarm)
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{
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struct pl031_local *ldata = dev_get_drvdata(dev);
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rtc_time_to_tm(readl(ldata->base + RTC_MR), &alarm->time);
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alarm->pending = readl(ldata->base + RTC_RIS) & RTC_BIT_AI;
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alarm->enabled = readl(ldata->base + RTC_IMSC) & RTC_BIT_AI;
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return 0;
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}
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static int pl031_set_alarm(struct device *dev, struct rtc_wkalrm *alarm)
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{
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struct pl031_local *ldata = dev_get_drvdata(dev);
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unsigned long time;
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int ret;
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/* At the moment, we can only deal with non-wildcarded alarm times. */
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ret = rtc_valid_tm(&alarm->time);
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if (ret == 0) {
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ret = rtc_tm_to_time(&alarm->time, &time);
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if (ret == 0) {
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writel(time, ldata->base + RTC_MR);
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pl031_alarm_irq_enable(dev, alarm->enabled);
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}
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}
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return ret;
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}
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/* Periodic interrupt is only available in ST variants. */
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static int pl031_irq_set_state(struct device *dev, int enabled)
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{
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struct pl031_local *ldata = dev_get_drvdata(dev);
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if (enabled == 1) {
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/* Clear any pending timer interrupt. */
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writel(RTC_BIT_PI, ldata->base + RTC_ICR);
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writel(readl(ldata->base + RTC_IMSC) | RTC_BIT_PI,
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ldata->base + RTC_IMSC);
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/* Now start the timer */
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writel(readl(ldata->base + RTC_TCR) | RTC_TCR_EN,
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ldata->base + RTC_TCR);
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} else {
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writel(readl(ldata->base + RTC_IMSC) & (~RTC_BIT_PI),
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ldata->base + RTC_IMSC);
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/* Also stop the timer */
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writel(readl(ldata->base + RTC_TCR) & (~RTC_TCR_EN),
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ldata->base + RTC_TCR);
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}
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/* Wait at least 1 RTC32 clock cycle to ensure next access
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* to RTC_TCR will succeed.
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*/
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udelay(40);
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return 0;
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}
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static int pl031_irq_set_freq(struct device *dev, int freq)
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{
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struct pl031_local *ldata = dev_get_drvdata(dev);
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/* Cant set timer if it is already enabled */
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if (readl(ldata->base + RTC_TCR) & RTC_TCR_EN) {
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dev_err(dev, "can't change frequency while timer enabled\n");
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return -EINVAL;
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}
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/* If self start bit in RTC_TCR is set timer will start here,
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* but we never set that bit. Instead we start the timer when
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* set_state is called with enabled == 1.
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*/
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writel(RTC_TIMER_FREQ / freq, ldata->base + RTC_TLR);
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return 0;
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}
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static int pl031_remove(struct amba_device *adev)
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{
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struct pl031_local *ldata = dev_get_drvdata(&adev->dev);
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amba_set_drvdata(adev, NULL);
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free_irq(adev->irq[0], ldata->rtc);
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rtc_device_unregister(ldata->rtc);
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iounmap(ldata->base);
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kfree(ldata);
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amba_release_regions(adev);
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return 0;
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}
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static int pl031_probe(struct amba_device *adev, struct amba_id *id)
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{
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int ret;
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struct pl031_local *ldata;
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struct rtc_class_ops *ops = id->data;
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ret = amba_request_regions(adev, NULL);
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if (ret)
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goto err_req;
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ldata = kzalloc(sizeof(struct pl031_local), GFP_KERNEL);
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if (!ldata) {
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ret = -ENOMEM;
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goto out;
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}
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ldata->base = ioremap(adev->res.start, resource_size(&adev->res));
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if (!ldata->base) {
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ret = -ENOMEM;
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goto out_no_remap;
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}
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amba_set_drvdata(adev, ldata);
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ldata->hw_designer = amba_manf(adev);
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ldata->hw_revision = amba_rev(adev);
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dev_dbg(&adev->dev, "designer ID = 0x%02x\n", ldata->hw_designer);
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dev_dbg(&adev->dev, "revision = 0x%01x\n", ldata->hw_revision);
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/* Enable the clockwatch on ST Variants */
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if ((ldata->hw_designer == AMBA_VENDOR_ST) &&
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(ldata->hw_revision > 1))
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writel(readl(ldata->base + RTC_CR) | RTC_CR_CWEN,
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ldata->base + RTC_CR);
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ldata->rtc = rtc_device_register("pl031", &adev->dev, ops,
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THIS_MODULE);
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if (IS_ERR(ldata->rtc)) {
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ret = PTR_ERR(ldata->rtc);
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goto out_no_rtc;
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}
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if (request_irq(adev->irq[0], pl031_interrupt,
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IRQF_DISABLED, "rtc-pl031", ldata)) {
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ret = -EIO;
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goto out_no_irq;
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}
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return 0;
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out_no_irq:
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rtc_device_unregister(ldata->rtc);
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out_no_rtc:
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iounmap(ldata->base);
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amba_set_drvdata(adev, NULL);
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out_no_remap:
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kfree(ldata);
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out:
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amba_release_regions(adev);
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err_req:
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return ret;
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}
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/* Operations for the original ARM version */
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static struct rtc_class_ops arm_pl031_ops = {
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.read_time = pl031_read_time,
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.set_time = pl031_set_time,
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.read_alarm = pl031_read_alarm,
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.set_alarm = pl031_set_alarm,
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.alarm_irq_enable = pl031_alarm_irq_enable,
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};
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/* The First ST derivative */
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static struct rtc_class_ops stv1_pl031_ops = {
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.read_time = pl031_read_time,
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.set_time = pl031_set_time,
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.read_alarm = pl031_read_alarm,
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.set_alarm = pl031_set_alarm,
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.alarm_irq_enable = pl031_alarm_irq_enable,
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.irq_set_state = pl031_irq_set_state,
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.irq_set_freq = pl031_irq_set_freq,
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};
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/* And the second ST derivative */
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static struct rtc_class_ops stv2_pl031_ops = {
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.read_time = pl031_stv2_read_time,
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.set_time = pl031_stv2_set_time,
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.read_alarm = pl031_stv2_read_alarm,
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.set_alarm = pl031_stv2_set_alarm,
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.alarm_irq_enable = pl031_alarm_irq_enable,
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.irq_set_state = pl031_irq_set_state,
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.irq_set_freq = pl031_irq_set_freq,
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};
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static struct amba_id pl031_ids[] = {
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{
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.id = 0x00041031,
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.mask = 0x000fffff,
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.data = &arm_pl031_ops,
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},
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/* ST Micro variants */
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{
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.id = 0x00180031,
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.mask = 0x00ffffff,
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.data = &stv1_pl031_ops,
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},
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{
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.id = 0x00280031,
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.mask = 0x00ffffff,
|
|
.data = &stv2_pl031_ops,
|
|
},
|
|
{0, 0},
|
|
};
|
|
|
|
static struct amba_driver pl031_driver = {
|
|
.drv = {
|
|
.name = "rtc-pl031",
|
|
},
|
|
.id_table = pl031_ids,
|
|
.probe = pl031_probe,
|
|
.remove = pl031_remove,
|
|
};
|
|
|
|
static int __init pl031_init(void)
|
|
{
|
|
return amba_driver_register(&pl031_driver);
|
|
}
|
|
|
|
static void __exit pl031_exit(void)
|
|
{
|
|
amba_driver_unregister(&pl031_driver);
|
|
}
|
|
|
|
module_init(pl031_init);
|
|
module_exit(pl031_exit);
|
|
|
|
MODULE_AUTHOR("Deepak Saxena <dsaxena@plexity.net");
|
|
MODULE_DESCRIPTION("ARM AMBA PL031 RTC Driver");
|
|
MODULE_LICENSE("GPL");
|