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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 503 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Enrico Weigelt <info@metux.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190602204653.811534538@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
395 lines
11 KiB
C
395 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* Copyright (c) 2014,2017 The Linux Foundation. All rights reserved.
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*/
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#ifndef __ADRENO_GPU_H__
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#define __ADRENO_GPU_H__
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#include <linux/firmware.h>
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#include <linux/iopoll.h>
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#include "msm_gpu.h"
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#include "adreno_common.xml.h"
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#include "adreno_pm4.xml.h"
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#define REG_ADRENO_DEFINE(_offset, _reg) [_offset] = (_reg) + 1
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#define REG_SKIP ~0
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#define REG_ADRENO_SKIP(_offset) [_offset] = REG_SKIP
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/**
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* adreno_regs: List of registers that are used in across all
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* 3D devices. Each device type has different offset value for the same
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* register, so an array of register offsets are declared for every device
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* and are indexed by the enumeration values defined in this enum
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*/
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enum adreno_regs {
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REG_ADRENO_CP_RB_BASE,
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REG_ADRENO_CP_RB_BASE_HI,
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REG_ADRENO_CP_RB_RPTR_ADDR,
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REG_ADRENO_CP_RB_RPTR_ADDR_HI,
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REG_ADRENO_CP_RB_RPTR,
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REG_ADRENO_CP_RB_WPTR,
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REG_ADRENO_CP_RB_CNTL,
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REG_ADRENO_REGISTER_MAX,
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};
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enum {
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ADRENO_FW_PM4 = 0,
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ADRENO_FW_SQE = 0, /* a6xx */
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ADRENO_FW_PFP = 1,
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ADRENO_FW_GMU = 1, /* a6xx */
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ADRENO_FW_GPMU = 2,
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ADRENO_FW_MAX,
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};
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enum adreno_quirks {
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ADRENO_QUIRK_TWO_PASS_USE_WFI = 1,
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ADRENO_QUIRK_FAULT_DETECT_MASK = 2,
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};
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struct adreno_rev {
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uint8_t core;
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uint8_t major;
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uint8_t minor;
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uint8_t patchid;
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};
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#define ADRENO_REV(core, major, minor, patchid) \
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((struct adreno_rev){ core, major, minor, patchid })
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struct adreno_gpu_funcs {
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struct msm_gpu_funcs base;
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int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
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};
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struct adreno_info {
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struct adreno_rev rev;
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uint32_t revn;
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const char *name;
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const char *fw[ADRENO_FW_MAX];
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uint32_t gmem;
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enum adreno_quirks quirks;
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struct msm_gpu *(*init)(struct drm_device *dev);
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const char *zapfw;
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u32 inactive_period;
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};
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const struct adreno_info *adreno_info(struct adreno_rev rev);
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struct adreno_gpu {
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struct msm_gpu base;
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struct adreno_rev rev;
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const struct adreno_info *info;
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uint32_t gmem; /* actual gmem size */
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uint32_t revn; /* numeric revision name */
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const struct adreno_gpu_funcs *funcs;
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/* interesting register offsets to dump: */
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const unsigned int *registers;
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/*
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* Are we loading fw from legacy path? Prior to addition
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* of gpu firmware to linux-firmware, the fw files were
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* placed in toplevel firmware directory, following qcom's
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* android kernel. But linux-firmware preferred they be
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* placed in a 'qcom' subdirectory.
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*
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* For backwards compatibility, we try first to load from
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* the new path, using request_firmware_direct() to avoid
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* any potential timeout waiting for usermode helper, then
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* fall back to the old path (with direct load). And
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* finally fall back to request_firmware() with the new
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* path to allow the usermode helper.
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*/
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enum {
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FW_LOCATION_UNKNOWN = 0,
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FW_LOCATION_NEW, /* /lib/firmware/qcom/$fwfile */
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FW_LOCATION_LEGACY, /* /lib/firmware/$fwfile */
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FW_LOCATION_HELPER,
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} fwloc;
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/* firmware: */
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const struct firmware *fw[ADRENO_FW_MAX];
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/*
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* Register offsets are different between some GPUs.
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* GPU specific offsets will be exported by GPU specific
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* code (a3xx_gpu.c) and stored in this common location.
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*/
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const unsigned int *reg_offsets;
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};
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#define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
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/* platform config data (ie. from DT, or pdata) */
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struct adreno_platform_config {
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struct adreno_rev rev;
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};
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#define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
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#define spin_until(X) ({ \
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int __ret = -ETIMEDOUT; \
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unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \
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do { \
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if (X) { \
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__ret = 0; \
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break; \
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} \
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} while (time_before(jiffies, __t)); \
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__ret; \
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})
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static inline bool adreno_is_a2xx(struct adreno_gpu *gpu)
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{
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return (gpu->revn < 300);
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}
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static inline bool adreno_is_a20x(struct adreno_gpu *gpu)
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{
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return (gpu->revn < 210);
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}
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static inline bool adreno_is_a225(struct adreno_gpu *gpu)
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{
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return gpu->revn == 225;
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}
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static inline bool adreno_is_a3xx(struct adreno_gpu *gpu)
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{
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return (gpu->revn >= 300) && (gpu->revn < 400);
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}
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static inline bool adreno_is_a305(struct adreno_gpu *gpu)
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{
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return gpu->revn == 305;
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}
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static inline bool adreno_is_a306(struct adreno_gpu *gpu)
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{
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/* yes, 307, because a305c is 306 */
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return gpu->revn == 307;
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}
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static inline bool adreno_is_a320(struct adreno_gpu *gpu)
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{
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return gpu->revn == 320;
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}
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static inline bool adreno_is_a330(struct adreno_gpu *gpu)
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{
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return gpu->revn == 330;
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}
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static inline bool adreno_is_a330v2(struct adreno_gpu *gpu)
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{
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return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
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}
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static inline bool adreno_is_a4xx(struct adreno_gpu *gpu)
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{
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return (gpu->revn >= 400) && (gpu->revn < 500);
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}
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static inline int adreno_is_a420(struct adreno_gpu *gpu)
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{
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return gpu->revn == 420;
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}
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static inline int adreno_is_a430(struct adreno_gpu *gpu)
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{
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return gpu->revn == 430;
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}
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static inline int adreno_is_a530(struct adreno_gpu *gpu)
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{
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return gpu->revn == 530;
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}
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int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
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const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,
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const char *fwname);
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struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
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const struct firmware *fw, u64 *iova);
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int adreno_hw_init(struct msm_gpu *gpu);
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void adreno_recover(struct msm_gpu *gpu);
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void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
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struct msm_file_private *ctx);
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void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
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bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
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#if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
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void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
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struct drm_printer *p);
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#endif
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void adreno_dump_info(struct msm_gpu *gpu);
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void adreno_dump(struct msm_gpu *gpu);
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void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords);
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struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu);
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int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
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struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
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int nr_rings);
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void adreno_gpu_cleanup(struct adreno_gpu *gpu);
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int adreno_load_fw(struct adreno_gpu *adreno_gpu);
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void adreno_gpu_state_destroy(struct msm_gpu_state *state);
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int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state);
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int adreno_gpu_state_put(struct msm_gpu_state *state);
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/*
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* For a5xx and a6xx targets load the zap shader that is used to pull the GPU
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* out of secure mode
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*/
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int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid);
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/* ringbuffer helpers (the parts that are adreno specific) */
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static inline void
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OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
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{
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adreno_wait_ring(ring, cnt+1);
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OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
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}
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/* no-op packet: */
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static inline void
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OUT_PKT2(struct msm_ringbuffer *ring)
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{
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adreno_wait_ring(ring, 1);
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OUT_RING(ring, CP_TYPE2_PKT);
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}
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static inline void
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OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
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{
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adreno_wait_ring(ring, cnt+1);
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OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
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}
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static inline u32 PM4_PARITY(u32 val)
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{
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return (0x9669 >> (0xF & (val ^
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(val >> 4) ^ (val >> 8) ^ (val >> 12) ^
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(val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^
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(val >> 28)))) & 1;
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}
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/* Maximum number of values that can be executed for one opcode */
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#define TYPE4_MAX_PAYLOAD 127
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#define PKT4(_reg, _cnt) \
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(CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \
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(((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27))
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static inline void
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OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
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{
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adreno_wait_ring(ring, cnt + 1);
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OUT_RING(ring, PKT4(regindx, cnt));
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}
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static inline void
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OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
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{
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adreno_wait_ring(ring, cnt + 1);
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OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) |
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((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23));
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}
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/*
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* adreno_reg_check() - Checks the validity of a register enum
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* @gpu: Pointer to struct adreno_gpu
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* @offset_name: The register enum that is checked
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*/
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static inline bool adreno_reg_check(struct adreno_gpu *gpu,
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enum adreno_regs offset_name)
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{
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if (offset_name >= REG_ADRENO_REGISTER_MAX ||
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!gpu->reg_offsets[offset_name]) {
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BUG();
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}
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/*
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* REG_SKIP is a special value that tell us that the register in
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* question isn't implemented on target but don't trigger a BUG(). This
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* is used to cleanly implement adreno_gpu_write64() and
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* adreno_gpu_read64() in a generic fashion
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*/
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if (gpu->reg_offsets[offset_name] == REG_SKIP)
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return false;
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return true;
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}
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static inline u32 adreno_gpu_read(struct adreno_gpu *gpu,
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enum adreno_regs offset_name)
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{
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u32 reg = gpu->reg_offsets[offset_name];
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u32 val = 0;
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if(adreno_reg_check(gpu,offset_name))
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val = gpu_read(&gpu->base, reg - 1);
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return val;
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}
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static inline void adreno_gpu_write(struct adreno_gpu *gpu,
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enum adreno_regs offset_name, u32 data)
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{
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u32 reg = gpu->reg_offsets[offset_name];
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if(adreno_reg_check(gpu, offset_name))
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gpu_write(&gpu->base, reg - 1, data);
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}
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struct msm_gpu *a2xx_gpu_init(struct drm_device *dev);
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struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
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struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
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struct msm_gpu *a5xx_gpu_init(struct drm_device *dev);
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struct msm_gpu *a6xx_gpu_init(struct drm_device *dev);
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static inline void adreno_gpu_write64(struct adreno_gpu *gpu,
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enum adreno_regs lo, enum adreno_regs hi, u64 data)
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{
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adreno_gpu_write(gpu, lo, lower_32_bits(data));
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adreno_gpu_write(gpu, hi, upper_32_bits(data));
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}
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static inline uint32_t get_wptr(struct msm_ringbuffer *ring)
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{
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return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2);
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}
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/*
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* Given a register and a count, return a value to program into
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* REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
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* registers starting at _reg.
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*
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* The register base needs to be a multiple of the length. If it is not, the
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* hardware will quietly mask off the bits for you and shift the size. For
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* example, if you intend the protection to start at 0x07 for a length of 4
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* (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might
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* expose registers you intended to protect!
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*/
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#define ADRENO_PROTECT_RW(_reg, _len) \
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((1 << 30) | (1 << 29) | \
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((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
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/*
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* Same as above, but allow reads over the range. For areas of mixed use (such
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* as performance counters) this allows us to protect a much larger range with a
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* single register
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*/
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#define ADRENO_PROTECT_RDONLY(_reg, _len) \
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((1 << 29) \
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((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
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#define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \
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readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \
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interval, timeout)
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#endif /* __ADRENO_GPU_H__ */
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