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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 and only version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 294 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190529141900.825281744@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
177 lines
3.8 KiB
C
177 lines
3.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
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*/
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#include <linux/types.h>
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#include <linux/debugfs.h>
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#include <drm/drm_print.h>
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#include "a5xx_gpu.h"
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static int pfp_print(struct msm_gpu *gpu, struct drm_printer *p)
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{
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int i;
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drm_printf(p, "PFP state:\n");
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for (i = 0; i < 36; i++) {
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gpu_write(gpu, REG_A5XX_CP_PFP_STAT_ADDR, i);
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drm_printf(p, " %02x: %08x\n", i,
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gpu_read(gpu, REG_A5XX_CP_PFP_STAT_DATA));
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}
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return 0;
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}
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static int me_print(struct msm_gpu *gpu, struct drm_printer *p)
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{
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int i;
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drm_printf(p, "ME state:\n");
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for (i = 0; i < 29; i++) {
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gpu_write(gpu, REG_A5XX_CP_ME_STAT_ADDR, i);
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drm_printf(p, " %02x: %08x\n", i,
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gpu_read(gpu, REG_A5XX_CP_ME_STAT_DATA));
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}
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return 0;
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}
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static int meq_print(struct msm_gpu *gpu, struct drm_printer *p)
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{
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int i;
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drm_printf(p, "MEQ state:\n");
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gpu_write(gpu, REG_A5XX_CP_MEQ_DBG_ADDR, 0);
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for (i = 0; i < 64; i++) {
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drm_printf(p, " %02x: %08x\n", i,
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gpu_read(gpu, REG_A5XX_CP_MEQ_DBG_DATA));
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}
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return 0;
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}
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static int roq_print(struct msm_gpu *gpu, struct drm_printer *p)
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{
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int i;
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drm_printf(p, "ROQ state:\n");
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gpu_write(gpu, REG_A5XX_CP_ROQ_DBG_ADDR, 0);
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for (i = 0; i < 512 / 4; i++) {
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uint32_t val[4];
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int j;
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for (j = 0; j < 4; j++)
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val[j] = gpu_read(gpu, REG_A5XX_CP_ROQ_DBG_DATA);
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drm_printf(p, " %02x: %08x %08x %08x %08x\n", i,
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val[0], val[1], val[2], val[3]);
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}
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return 0;
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}
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static int show(struct seq_file *m, void *arg)
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{
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struct drm_info_node *node = (struct drm_info_node *) m->private;
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struct drm_device *dev = node->minor->dev;
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struct msm_drm_private *priv = dev->dev_private;
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struct drm_printer p = drm_seq_file_printer(m);
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int (*show)(struct msm_gpu *gpu, struct drm_printer *p) =
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node->info_ent->data;
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return show(priv->gpu, &p);
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}
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#define ENT(n) { .name = #n, .show = show, .data = n ##_print }
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static struct drm_info_list a5xx_debugfs_list[] = {
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ENT(pfp),
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ENT(me),
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ENT(meq),
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ENT(roq),
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};
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/* for debugfs files that can be written to, we can't use drm helper: */
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static int
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reset_set(void *data, u64 val)
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{
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struct drm_device *dev = data;
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struct msm_drm_private *priv = dev->dev_private;
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struct msm_gpu *gpu = priv->gpu;
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struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
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struct a5xx_gpu *a5xx_gpu = to_a5xx_gpu(adreno_gpu);
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if (!capable(CAP_SYS_ADMIN))
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return -EINVAL;
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/* TODO do we care about trying to make sure the GPU is idle?
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* Since this is just a debug feature limited to CAP_SYS_ADMIN,
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* maybe it is fine to let the user keep both pieces if they
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* try to reset an active GPU.
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*/
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mutex_lock(&dev->struct_mutex);
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release_firmware(adreno_gpu->fw[ADRENO_FW_PM4]);
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adreno_gpu->fw[ADRENO_FW_PM4] = NULL;
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release_firmware(adreno_gpu->fw[ADRENO_FW_PFP]);
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adreno_gpu->fw[ADRENO_FW_PFP] = NULL;
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if (a5xx_gpu->pm4_bo) {
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msm_gem_unpin_iova(a5xx_gpu->pm4_bo, gpu->aspace);
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drm_gem_object_put(a5xx_gpu->pm4_bo);
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a5xx_gpu->pm4_bo = NULL;
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}
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if (a5xx_gpu->pfp_bo) {
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msm_gem_unpin_iova(a5xx_gpu->pfp_bo, gpu->aspace);
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drm_gem_object_put(a5xx_gpu->pfp_bo);
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a5xx_gpu->pfp_bo = NULL;
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}
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gpu->needs_hw_init = true;
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pm_runtime_get_sync(&gpu->pdev->dev);
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gpu->funcs->recover(gpu);
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pm_runtime_put_sync(&gpu->pdev->dev);
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mutex_unlock(&dev->struct_mutex);
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return 0;
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}
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DEFINE_SIMPLE_ATTRIBUTE(reset_fops, NULL, reset_set, "%llx\n");
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int a5xx_debugfs_init(struct msm_gpu *gpu, struct drm_minor *minor)
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{
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struct drm_device *dev;
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struct dentry *ent;
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int ret;
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if (!minor)
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return 0;
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dev = minor->dev;
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ret = drm_debugfs_create_files(a5xx_debugfs_list,
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ARRAY_SIZE(a5xx_debugfs_list),
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minor->debugfs_root, minor);
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if (ret) {
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DRM_DEV_ERROR(dev->dev, "could not install a5xx_debugfs_list\n");
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return ret;
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}
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ent = debugfs_create_file("reset", S_IWUGO,
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minor->debugfs_root,
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dev, &reset_fops);
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if (!ent)
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return -ENOMEM;
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return 0;
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}
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