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0bbe6b5a73
Fixes the TCM initialisation code to handle TCM banks that are present but inaccessible due to TrustZone configuration. This is the default case when enabling the non-secure world. It may also be the case that that the user decided to use TCM for TrustZone. This change has exposed a bug in handling of TCM where no TCM bank was usable (the 0 size TCM case). This change addresses the resulting hang. This code only handles the ARMv6 TCMTR register format, and will not work correctly on boards that use the ARMv7 (or any other) format. This is handled by performing an early exit from the initialisation function when the TCMTR reports any format other than v6. Signed-off-by: Michael van der Westhuizen <michael@smart-africa.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Dave Martin <Dave.Martin@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
435 lines
12 KiB
C
435 lines
12 KiB
C
/*
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* Copyright (C) 2008-2009 ST-Ericsson AB
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* License terms: GNU General Public License (GPL) version 2
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* TCM memory handling for ARM systems
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*
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* Author: Linus Walleij <linus.walleij@stericsson.com>
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* Author: Rickard Andersson <rickard.andersson@stericsson.com>
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/stddef.h>
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#include <linux/ioport.h>
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#include <linux/genalloc.h>
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#include <linux/string.h> /* memcpy */
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#include <asm/cputype.h>
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#include <asm/mach/map.h>
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#include <asm/memory.h>
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#include <asm/system_info.h>
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#include <asm/traps.h>
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#define TCMTR_FORMAT_MASK 0xe0000000U
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static struct gen_pool *tcm_pool;
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static bool dtcm_present;
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static bool itcm_present;
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/* TCM section definitions from the linker */
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extern char __itcm_start, __sitcm_text, __eitcm_text;
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extern char __dtcm_start, __sdtcm_data, __edtcm_data;
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/* These will be increased as we run */
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u32 dtcm_end = DTCM_OFFSET;
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u32 itcm_end = ITCM_OFFSET;
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/*
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* TCM memory resources
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*/
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static struct resource dtcm_res = {
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.name = "DTCM RAM",
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.start = DTCM_OFFSET,
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.end = DTCM_OFFSET,
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.flags = IORESOURCE_MEM
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};
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static struct resource itcm_res = {
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.name = "ITCM RAM",
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.start = ITCM_OFFSET,
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.end = ITCM_OFFSET,
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.flags = IORESOURCE_MEM
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};
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static struct map_desc dtcm_iomap[] __initdata = {
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{
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.virtual = DTCM_OFFSET,
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.pfn = __phys_to_pfn(DTCM_OFFSET),
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.length = 0,
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.type = MT_MEMORY_RW_DTCM
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}
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};
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static struct map_desc itcm_iomap[] __initdata = {
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{
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.virtual = ITCM_OFFSET,
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.pfn = __phys_to_pfn(ITCM_OFFSET),
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.length = 0,
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.type = MT_MEMORY_RWX_ITCM,
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}
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};
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/*
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* Allocate a chunk of TCM memory
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*/
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void *tcm_alloc(size_t len)
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{
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unsigned long vaddr;
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if (!tcm_pool)
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return NULL;
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vaddr = gen_pool_alloc(tcm_pool, len);
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if (!vaddr)
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return NULL;
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return (void *) vaddr;
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}
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EXPORT_SYMBOL(tcm_alloc);
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/*
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* Free a chunk of TCM memory
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*/
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void tcm_free(void *addr, size_t len)
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{
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gen_pool_free(tcm_pool, (unsigned long) addr, len);
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}
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EXPORT_SYMBOL(tcm_free);
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bool tcm_dtcm_present(void)
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{
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return dtcm_present;
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}
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EXPORT_SYMBOL(tcm_dtcm_present);
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bool tcm_itcm_present(void)
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{
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return itcm_present;
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}
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EXPORT_SYMBOL(tcm_itcm_present);
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static int __init setup_tcm_bank(u8 type, u8 bank, u8 banks,
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u32 *offset)
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{
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const int tcm_sizes[16] = { 0, -1, -1, 4, 8, 16, 32, 64, 128,
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256, 512, 1024, -1, -1, -1, -1 };
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u32 tcm_region;
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int tcm_size;
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/*
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* If there are more than one TCM bank of this type,
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* select the TCM bank to operate on in the TCM selection
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* register.
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*/
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if (banks > 1)
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asm("mcr p15, 0, %0, c9, c2, 0"
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: /* No output operands */
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: "r" (bank));
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/* Read the special TCM region register c9, 0 */
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if (!type)
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asm("mrc p15, 0, %0, c9, c1, 0"
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: "=r" (tcm_region));
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else
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asm("mrc p15, 0, %0, c9, c1, 1"
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: "=r" (tcm_region));
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tcm_size = tcm_sizes[(tcm_region >> 2) & 0x0f];
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if (tcm_size < 0) {
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pr_err("CPU: %sTCM%d of unknown size\n",
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type ? "I" : "D", bank);
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return -EINVAL;
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} else if (tcm_size > 32) {
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pr_err("CPU: %sTCM%d larger than 32k found\n",
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type ? "I" : "D", bank);
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return -EINVAL;
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} else {
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pr_info("CPU: found %sTCM%d %dk @ %08x, %senabled\n",
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type ? "I" : "D",
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bank,
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tcm_size,
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(tcm_region & 0xfffff000U),
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(tcm_region & 1) ? "" : "not ");
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}
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/* Not much fun you can do with a size 0 bank */
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if (tcm_size == 0)
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return 0;
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/* Force move the TCM bank to where we want it, enable */
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tcm_region = *offset | (tcm_region & 0x00000ffeU) | 1;
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if (!type)
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asm("mcr p15, 0, %0, c9, c1, 0"
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: /* No output operands */
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: "r" (tcm_region));
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else
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asm("mcr p15, 0, %0, c9, c1, 1"
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: /* No output operands */
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: "r" (tcm_region));
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/* Increase offset */
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*offset += (tcm_size << 10);
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pr_info("CPU: moved %sTCM%d %dk to %08x, enabled\n",
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type ? "I" : "D",
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bank,
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tcm_size,
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(tcm_region & 0xfffff000U));
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return 0;
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}
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/*
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* When we are running in the non-secure world and the secure world
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* has not explicitly given us access to the TCM we will get an
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* undefined error when reading the TCM region register in the
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* setup_tcm_bank function (above).
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*
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* There are two variants of this register read that we need to trap,
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* the read for the data TCM and the read for the instruction TCM:
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* c0370628: ee196f11 mrc 15, 0, r6, cr9, cr1, {0}
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* c0370674: ee196f31 mrc 15, 0, r6, cr9, cr1, {1}
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*
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* Our undef hook mask explicitly matches all fields of the encoded
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* instruction other than the destination register. The mask also
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* only allows operand 2 to have the values 0 or 1.
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*
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* The undefined hook is defined as __init and __initdata, and therefore
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* must be removed before tcm_init returns.
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*
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* In this particular case (MRC with ARM condition code ALways) the
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* Thumb-2 and ARM instruction encoding are identical, so this hook
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* will work on a Thumb-2 kernel.
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*
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* See A8.8.107, DDI0406C_C ARM Architecture Reference Manual, Encoding
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* T1/A1 for the bit-by-bit details.
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*
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* mrc p15, 0, XX, c9, c1, 0
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* mrc p15, 0, XX, c9, c1, 1
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* | | | | | | | +---- opc2 0|1 = 000|001
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* | | | | | | +------- CRm 0 = 0001
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* | | | | | +----------- CRn 0 = 1001
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* | | | | +--------------- Rt ? = ????
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* | | | +------------------- opc1 0 = 000
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* | | +----------------------- coproc 15 = 1111
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* | +-------------------------- condition ALways = 1110
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* +----------------------------- instruction MRC = 1110
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*
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* Encoding this as per A8.8.107 of DDI0406C, Encoding T1/A1, yields:
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* 1111 1111 1111 1111 0000 1111 1101 1111 Required Mask
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* 1110 1110 0001 1001 ???? 1111 0001 0001 mrc p15, 0, XX, c9, c1, 0
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* 1110 1110 0001 1001 ???? 1111 0011 0001 mrc p15, 0, XX, c9, c1, 1
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* [ ] [ ] [ ]| [ ] [ ] [ ] [ ]| +--- CRm
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* | | | | | | | | +----- SBO
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* | | | | | | | +------- opc2
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* | | | | | | +----------- coproc
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* | | | | | +---------------- Rt
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* | | | | +--------------------- CRn
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* | | | +------------------------- SBO
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* | | +--------------------------- opc1
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* | +------------------------------- instruction
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* +------------------------------------ condition
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*/
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#define TCM_REGION_READ_MASK 0xffff0fdf
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#define TCM_REGION_READ_INSTR 0xee190f11
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#define DEST_REG_SHIFT 12
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#define DEST_REG_MASK 0xf
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static int __init tcm_handler(struct pt_regs *regs, unsigned int instr)
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{
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regs->uregs[(instr >> DEST_REG_SHIFT) & DEST_REG_MASK] = 0;
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regs->ARM_pc += 4;
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return 0;
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}
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static struct undef_hook tcm_hook __initdata = {
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.instr_mask = TCM_REGION_READ_MASK,
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.instr_val = TCM_REGION_READ_INSTR,
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.cpsr_mask = MODE_MASK,
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.cpsr_val = SVC_MODE,
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.fn = tcm_handler
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};
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/*
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* This initializes the TCM memory
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*/
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void __init tcm_init(void)
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{
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u32 tcm_status;
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u8 dtcm_banks;
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u8 itcm_banks;
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size_t dtcm_code_sz = &__edtcm_data - &__sdtcm_data;
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size_t itcm_code_sz = &__eitcm_text - &__sitcm_text;
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char *start;
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char *end;
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char *ram;
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int ret;
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int i;
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/*
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* Prior to ARMv5 there is no TCM, and trying to read the status
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* register will hang the processor.
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*/
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if (cpu_architecture() < CPU_ARCH_ARMv5) {
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if (dtcm_code_sz || itcm_code_sz)
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pr_info("CPU TCM: %u bytes of DTCM and %u bytes of "
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"ITCM code compiled in, but no TCM present "
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"in pre-v5 CPU\n", dtcm_code_sz, itcm_code_sz);
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return;
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}
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tcm_status = read_cpuid_tcmstatus();
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/*
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* This code only supports v6-compatible TCMTR implementations.
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*/
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if (tcm_status & TCMTR_FORMAT_MASK)
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return;
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dtcm_banks = (tcm_status >> 16) & 0x03;
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itcm_banks = (tcm_status & 0x03);
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register_undef_hook(&tcm_hook);
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/* Values greater than 2 for D/ITCM banks are "reserved" */
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if (dtcm_banks > 2)
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dtcm_banks = 0;
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if (itcm_banks > 2)
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itcm_banks = 0;
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/* Setup DTCM if present */
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if (dtcm_banks > 0) {
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for (i = 0; i < dtcm_banks; i++) {
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ret = setup_tcm_bank(0, i, dtcm_banks, &dtcm_end);
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if (ret)
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goto unregister;
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}
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/* This means you compiled more code than fits into DTCM */
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if (dtcm_code_sz > (dtcm_end - DTCM_OFFSET)) {
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pr_info("CPU DTCM: %u bytes of code compiled to "
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"DTCM but only %lu bytes of DTCM present\n",
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dtcm_code_sz, (dtcm_end - DTCM_OFFSET));
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goto no_dtcm;
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}
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/*
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* This means that the DTCM sizes were 0 or the DTCM banks
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* were inaccessible due to TrustZone configuration.
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*/
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if (!(dtcm_end - DTCM_OFFSET))
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goto no_dtcm;
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dtcm_res.end = dtcm_end - 1;
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request_resource(&iomem_resource, &dtcm_res);
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dtcm_iomap[0].length = dtcm_end - DTCM_OFFSET;
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iotable_init(dtcm_iomap, 1);
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/* Copy data from RAM to DTCM */
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start = &__sdtcm_data;
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end = &__edtcm_data;
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ram = &__dtcm_start;
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memcpy(start, ram, dtcm_code_sz);
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pr_debug("CPU DTCM: copied data from %p - %p\n",
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start, end);
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dtcm_present = true;
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} else if (dtcm_code_sz) {
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pr_info("CPU DTCM: %u bytes of code compiled to DTCM but no "
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"DTCM banks present in CPU\n", dtcm_code_sz);
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}
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no_dtcm:
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/* Setup ITCM if present */
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if (itcm_banks > 0) {
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for (i = 0; i < itcm_banks; i++) {
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ret = setup_tcm_bank(1, i, itcm_banks, &itcm_end);
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if (ret)
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goto unregister;
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}
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/* This means you compiled more code than fits into ITCM */
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if (itcm_code_sz > (itcm_end - ITCM_OFFSET)) {
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pr_info("CPU ITCM: %u bytes of code compiled to "
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"ITCM but only %lu bytes of ITCM present\n",
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itcm_code_sz, (itcm_end - ITCM_OFFSET));
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goto unregister;
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}
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/*
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* This means that the ITCM sizes were 0 or the ITCM banks
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* were inaccessible due to TrustZone configuration.
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*/
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if (!(itcm_end - ITCM_OFFSET))
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goto unregister;
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itcm_res.end = itcm_end - 1;
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request_resource(&iomem_resource, &itcm_res);
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itcm_iomap[0].length = itcm_end - ITCM_OFFSET;
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iotable_init(itcm_iomap, 1);
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/* Copy code from RAM to ITCM */
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start = &__sitcm_text;
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end = &__eitcm_text;
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ram = &__itcm_start;
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memcpy(start, ram, itcm_code_sz);
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pr_debug("CPU ITCM: copied code from %p - %p\n",
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start, end);
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itcm_present = true;
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} else if (itcm_code_sz) {
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pr_info("CPU ITCM: %u bytes of code compiled to ITCM but no "
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"ITCM banks present in CPU\n", itcm_code_sz);
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}
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unregister:
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unregister_undef_hook(&tcm_hook);
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}
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/*
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* This creates the TCM memory pool and has to be done later,
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* during the core_initicalls, since the allocator is not yet
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* up and running when the first initialization runs.
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*/
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static int __init setup_tcm_pool(void)
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{
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u32 dtcm_pool_start = (u32) &__edtcm_data;
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u32 itcm_pool_start = (u32) &__eitcm_text;
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int ret;
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/*
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* Set up malloc pool, 2^2 = 4 bytes granularity since
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* the TCM is sometimes just 4 KiB. NB: pages and cache
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* line alignments does not matter in TCM!
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*/
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tcm_pool = gen_pool_create(2, -1);
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pr_debug("Setting up TCM memory pool\n");
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/* Add the rest of DTCM to the TCM pool */
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if (dtcm_present) {
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if (dtcm_pool_start < dtcm_end) {
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ret = gen_pool_add(tcm_pool, dtcm_pool_start,
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dtcm_end - dtcm_pool_start, -1);
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if (ret) {
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pr_err("CPU DTCM: could not add DTCM " \
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"remainder to pool!\n");
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return ret;
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}
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pr_debug("CPU DTCM: Added %08x bytes @ %08x to " \
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"the TCM memory pool\n",
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dtcm_end - dtcm_pool_start,
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dtcm_pool_start);
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}
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}
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/* Add the rest of ITCM to the TCM pool */
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if (itcm_present) {
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if (itcm_pool_start < itcm_end) {
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ret = gen_pool_add(tcm_pool, itcm_pool_start,
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itcm_end - itcm_pool_start, -1);
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if (ret) {
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pr_err("CPU ITCM: could not add ITCM " \
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"remainder to pool!\n");
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return ret;
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}
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pr_debug("CPU ITCM: Added %08x bytes @ %08x to " \
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"the TCM memory pool\n",
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itcm_end - itcm_pool_start,
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itcm_pool_start);
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}
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}
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return 0;
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}
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core_initcall(setup_tcm_pool);
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