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The PLL loop filter/gain can be located in a separate register on some SoCs. Split these off into a separate variable, so that an offset can be added if necessary. Also, make the necessary modifications to the Cygnus and NSP drivers for this change. Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> |
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clk-bcm281xx.c | ||
clk-bcm21664.c | ||
clk-cygnus.c | ||
clk-iproc-armpll.c | ||
clk-iproc-asiu.c | ||
clk-iproc-pll.c | ||
clk-iproc.h | ||
clk-kona-setup.c | ||
clk-kona.c | ||
clk-kona.h | ||
clk-nsp.c | ||
Kconfig | ||
Makefile |