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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
350 lines
11 KiB
C
350 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2014 Samsung Electronics Co., Ltd.
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* Author: Ajay Kumar <ajaykumar.rs@samsung.com>
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*/
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#ifndef EXYNOS_REGS_DECON7_H
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#define EXYNOS_REGS_DECON7_H
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/* VIDCON0 */
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#define VIDCON0 0x00
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#define VIDCON0_SWRESET (1 << 28)
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#define VIDCON0_DECON_STOP_STATUS (1 << 2)
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#define VIDCON0_ENVID (1 << 1)
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#define VIDCON0_ENVID_F (1 << 0)
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/* VIDOUTCON0 */
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#define VIDOUTCON0 0x4
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#define VIDOUTCON0_DUAL_MASK (0x3 << 24)
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#define VIDOUTCON0_DUAL_ON (0x3 << 24)
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#define VIDOUTCON0_DISP_IF_1_ON (0x2 << 24)
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#define VIDOUTCON0_DISP_IF_0_ON (0x1 << 24)
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#define VIDOUTCON0_DUAL_OFF (0x0 << 24)
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#define VIDOUTCON0_IF_SHIFT 23
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#define VIDOUTCON0_IF_MASK (0x1 << 23)
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#define VIDOUTCON0_RGBIF (0x0 << 23)
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#define VIDOUTCON0_I80IF (0x1 << 23)
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/* VIDCON3 */
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#define VIDCON3 0x8
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/* VIDCON4 */
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#define VIDCON4 0xC
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#define VIDCON4_FIFOCNT_START_EN (1 << 0)
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/* VCLKCON0 */
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#define VCLKCON0 0x10
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#define VCLKCON0_CLKVALUP (1 << 8)
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#define VCLKCON0_VCLKFREE (1 << 0)
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/* VCLKCON */
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#define VCLKCON1 0x14
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#define VCLKCON1_CLKVAL_NUM_VCLK(val) (((val) & 0xff) << 0)
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#define VCLKCON2 0x18
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/* SHADOWCON */
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#define SHADOWCON 0x30
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#define SHADOWCON_WINx_PROTECT(_win) (1 << (10 + (_win)))
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/* WINCONx */
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#define WINCON(_win) (0x50 + ((_win) * 4))
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#define WINCONx_BUFSTATUS (0x3 << 30)
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#define WINCONx_BUFSEL_MASK (0x3 << 28)
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#define WINCONx_BUFSEL_SHIFT 28
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#define WINCONx_TRIPLE_BUF_MODE (0x1 << 18)
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#define WINCONx_DOUBLE_BUF_MODE (0x0 << 18)
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#define WINCONx_BURSTLEN_16WORD (0x0 << 11)
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#define WINCONx_BURSTLEN_8WORD (0x1 << 11)
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#define WINCONx_BURSTLEN_MASK (0x1 << 11)
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#define WINCONx_BURSTLEN_SHIFT 11
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#define WINCONx_BLD_PLANE (0 << 8)
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#define WINCONx_BLD_PIX (1 << 8)
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#define WINCONx_ALPHA_MUL (1 << 7)
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#define WINCONx_BPPMODE_MASK (0xf << 2)
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#define WINCONx_BPPMODE_SHIFT 2
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#define WINCONx_BPPMODE_16BPP_565 (0x8 << 2)
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#define WINCONx_BPPMODE_24BPP_BGRx (0x7 << 2)
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#define WINCONx_BPPMODE_24BPP_RGBx (0x6 << 2)
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#define WINCONx_BPPMODE_24BPP_xBGR (0x5 << 2)
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#define WINCONx_BPPMODE_24BPP_xRGB (0x4 << 2)
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#define WINCONx_BPPMODE_32BPP_BGRA (0x3 << 2)
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#define WINCONx_BPPMODE_32BPP_RGBA (0x2 << 2)
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#define WINCONx_BPPMODE_32BPP_ABGR (0x1 << 2)
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#define WINCONx_BPPMODE_32BPP_ARGB (0x0 << 2)
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#define WINCONx_ALPHA_SEL (1 << 1)
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#define WINCONx_ENWIN (1 << 0)
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#define WINCON1_ALPHA_MUL_F (1 << 7)
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#define WINCON2_ALPHA_MUL_F (1 << 7)
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#define WINCON3_ALPHA_MUL_F (1 << 7)
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#define WINCON4_ALPHA_MUL_F (1 << 7)
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/* VIDOSDxH: The height for the OSD image(READ ONLY)*/
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#define VIDOSD_H(_x) (0x80 + ((_x) * 4))
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/* Frame buffer start addresses: VIDWxxADD0n */
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#define VIDW_BUF_START(_win) (0x80 + ((_win) * 0x10))
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#define VIDW_BUF_START1(_win) (0x84 + ((_win) * 0x10))
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#define VIDW_BUF_START2(_win) (0x88 + ((_win) * 0x10))
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#define VIDW_WHOLE_X(_win) (0x0130 + ((_win) * 8))
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#define VIDW_WHOLE_Y(_win) (0x0134 + ((_win) * 8))
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#define VIDW_OFFSET_X(_win) (0x0170 + ((_win) * 8))
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#define VIDW_OFFSET_Y(_win) (0x0174 + ((_win) * 8))
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#define VIDW_BLKOFFSET(_win) (0x01B0 + ((_win) * 4))
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#define VIDW_BLKSIZE(win) (0x0200 + ((_win) * 4))
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/* Interrupt controls register */
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#define VIDINTCON2 0x228
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#define VIDINTCON1_INTEXTRA1_EN (1 << 1)
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#define VIDINTCON1_INTEXTRA0_EN (1 << 0)
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/* Interrupt controls and status register */
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#define VIDINTCON3 0x22C
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#define VIDINTCON1_INTEXTRA1_PEND (1 << 1)
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#define VIDINTCON1_INTEXTRA0_PEND (1 << 0)
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/* VIDOSDxA ~ VIDOSDxE */
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#define VIDOSD_BASE 0x230
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#define OSD_STRIDE 0x20
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#define VIDOSD_A(_win) (VIDOSD_BASE + \
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((_win) * OSD_STRIDE) + 0x00)
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#define VIDOSD_B(_win) (VIDOSD_BASE + \
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((_win) * OSD_STRIDE) + 0x04)
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#define VIDOSD_C(_win) (VIDOSD_BASE + \
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((_win) * OSD_STRIDE) + 0x08)
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#define VIDOSD_D(_win) (VIDOSD_BASE + \
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((_win) * OSD_STRIDE) + 0x0C)
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#define VIDOSD_E(_win) (VIDOSD_BASE + \
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((_win) * OSD_STRIDE) + 0x10)
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#define VIDOSDxA_TOPLEFT_X_MASK (0x1fff << 13)
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#define VIDOSDxA_TOPLEFT_X_SHIFT 13
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#define VIDOSDxA_TOPLEFT_X_LIMIT 0x1fff
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#define VIDOSDxA_TOPLEFT_X(_x) (((_x) & 0x1fff) << 13)
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#define VIDOSDxA_TOPLEFT_Y_MASK (0x1fff << 0)
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#define VIDOSDxA_TOPLEFT_Y_SHIFT 0
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#define VIDOSDxA_TOPLEFT_Y_LIMIT 0x1fff
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#define VIDOSDxA_TOPLEFT_Y(_x) (((_x) & 0x1fff) << 0)
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#define VIDOSDxB_BOTRIGHT_X_MASK (0x1fff << 13)
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#define VIDOSDxB_BOTRIGHT_X_SHIFT 13
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#define VIDOSDxB_BOTRIGHT_X_LIMIT 0x1fff
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#define VIDOSDxB_BOTRIGHT_X(_x) (((_x) & 0x1fff) << 13)
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#define VIDOSDxB_BOTRIGHT_Y_MASK (0x1fff << 0)
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#define VIDOSDxB_BOTRIGHT_Y_SHIFT 0
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#define VIDOSDxB_BOTRIGHT_Y_LIMIT 0x1fff
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#define VIDOSDxB_BOTRIGHT_Y(_x) (((_x) & 0x1fff) << 0)
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#define VIDOSDxC_ALPHA0_R_F(_x) (((_x) & 0xFF) << 16)
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#define VIDOSDxC_ALPHA0_G_F(_x) (((_x) & 0xFF) << 8)
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#define VIDOSDxC_ALPHA0_B_F(_x) (((_x) & 0xFF) << 0)
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#define VIDOSDxD_ALPHA1_R_F(_x) (((_x) & 0xFF) << 16)
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#define VIDOSDxD_ALPHA1_G_F(_x) (((_x) & 0xFF) << 8)
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#define VIDOSDxD_ALPHA1_B_F(_x) (((_x) & 0xFF) >> 0)
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/* Window MAP (Color map) */
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#define WINxMAP(_win) (0x340 + ((_win) * 4))
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#define WINxMAP_MAP (1 << 24)
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#define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0)
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#define WINxMAP_MAP_COLOUR_SHIFT 0
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#define WINxMAP_MAP_COLOUR_LIMIT 0xffffff
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#define WINxMAP_MAP_COLOUR(_x) ((_x) << 0)
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/* Window colour-key control registers */
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#define WKEYCON 0x370
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#define WKEYCON0 0x00
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#define WKEYCON1 0x04
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#define WxKEYCON0_KEYBL_EN (1 << 26)
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#define WxKEYCON0_KEYEN_F (1 << 25)
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#define WxKEYCON0_DIRCON (1 << 24)
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#define WxKEYCON0_COMPKEY_MASK (0xffffff << 0)
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#define WxKEYCON0_COMPKEY_SHIFT 0
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#define WxKEYCON0_COMPKEY_LIMIT 0xffffff
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#define WxKEYCON0_COMPKEY(_x) ((_x) << 0)
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#define WxKEYCON1_COLVAL_MASK (0xffffff << 0)
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#define WxKEYCON1_COLVAL_SHIFT 0
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#define WxKEYCON1_COLVAL_LIMIT 0xffffff
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#define WxKEYCON1_COLVAL(_x) ((_x) << 0)
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/* color key control register for hardware window 1 ~ 4. */
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#define WKEYCON0_BASE(x) ((WKEYCON + WKEYCON0) + ((x - 1) * 8))
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/* color key value register for hardware window 1 ~ 4. */
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#define WKEYCON1_BASE(x) ((WKEYCON + WKEYCON1) + ((x - 1) * 8))
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/* Window KEY Alpha value */
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#define WxKEYALPHA(_win) (0x3A0 + (((_win) - 1) * 0x4))
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#define Wx_KEYALPHA_R_F_SHIFT 16
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#define Wx_KEYALPHA_G_F_SHIFT 8
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#define Wx_KEYALPHA_B_F_SHIFT 0
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/* Blending equation */
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#define BLENDE(_win) (0x03C0 + ((_win) * 4))
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#define BLENDE_COEF_ZERO 0x0
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#define BLENDE_COEF_ONE 0x1
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#define BLENDE_COEF_ALPHA_A 0x2
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#define BLENDE_COEF_ONE_MINUS_ALPHA_A 0x3
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#define BLENDE_COEF_ALPHA_B 0x4
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#define BLENDE_COEF_ONE_MINUS_ALPHA_B 0x5
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#define BLENDE_COEF_ALPHA0 0x6
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#define BLENDE_COEF_A 0xA
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#define BLENDE_COEF_ONE_MINUS_A 0xB
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#define BLENDE_COEF_B 0xC
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#define BLENDE_COEF_ONE_MINUS_B 0xD
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#define BLENDE_Q_FUNC(_v) ((_v) << 18)
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#define BLENDE_P_FUNC(_v) ((_v) << 12)
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#define BLENDE_B_FUNC(_v) ((_v) << 6)
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#define BLENDE_A_FUNC(_v) ((_v) << 0)
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/* Blending equation control */
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#define BLENDCON 0x3D8
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#define BLENDCON_NEW_MASK (1 << 0)
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#define BLENDCON_NEW_8BIT_ALPHA_VALUE (1 << 0)
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#define BLENDCON_NEW_4BIT_ALPHA_VALUE (0 << 0)
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/* Interrupt control register */
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#define VIDINTCON0 0x500
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#define VIDINTCON0_WAKEUP_MASK (0x3f << 26)
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#define VIDINTCON0_INTEXTRAEN (1 << 21)
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#define VIDINTCON0_FRAMESEL0_SHIFT 15
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#define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15)
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#define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15)
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#define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15)
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#define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15)
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#define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15)
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#define VIDINTCON0_INT_FRAME (1 << 11)
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#define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 3)
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#define VIDINTCON0_FIFOLEVEL_SHIFT 3
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#define VIDINTCON0_FIFOLEVEL_EMPTY (0x0 << 3)
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#define VIDINTCON0_FIFOLEVEL_TO25PC (0x1 << 3)
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#define VIDINTCON0_FIFOLEVEL_TO50PC (0x2 << 3)
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#define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 3)
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#define VIDINTCON0_FIFOSEL_MAIN_EN (1 << 1)
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#define VIDINTCON0_INT_FIFO (1 << 1)
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#define VIDINTCON0_INT_ENABLE (1 << 0)
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/* Interrupt controls and status register */
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#define VIDINTCON1 0x504
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#define VIDINTCON1_INT_EXTRA (1 << 3)
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#define VIDINTCON1_INT_I80 (1 << 2)
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#define VIDINTCON1_INT_FRAME (1 << 1)
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#define VIDINTCON1_INT_FIFO (1 << 0)
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/* VIDCON1 */
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#define VIDCON1(_x) (0x0600 + ((_x) * 0x50))
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#define VIDCON1_LINECNT_GET(_v) (((_v) >> 17) & 0x1fff)
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#define VIDCON1_VCLK_MASK (0x3 << 9)
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#define VIDCON1_VCLK_HOLD (0x0 << 9)
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#define VIDCON1_VCLK_RUN (0x1 << 9)
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#define VIDCON1_VCLK_RUN_VDEN_DISABLE (0x3 << 9)
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#define VIDCON1_RGB_ORDER_O_MASK (0x7 << 4)
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#define VIDCON1_RGB_ORDER_O_RGB (0x0 << 4)
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#define VIDCON1_RGB_ORDER_O_GBR (0x1 << 4)
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#define VIDCON1_RGB_ORDER_O_BRG (0x2 << 4)
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#define VIDCON1_RGB_ORDER_O_BGR (0x4 << 4)
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#define VIDCON1_RGB_ORDER_O_RBG (0x5 << 4)
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#define VIDCON1_RGB_ORDER_O_GRB (0x6 << 4)
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/* VIDTCON0 */
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#define VIDTCON0 0x610
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#define VIDTCON0_VBPD_MASK (0xffff << 16)
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#define VIDTCON0_VBPD_SHIFT 16
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#define VIDTCON0_VBPD_LIMIT 0xffff
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#define VIDTCON0_VBPD(_x) ((_x) << 16)
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#define VIDTCON0_VFPD_MASK (0xffff << 0)
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#define VIDTCON0_VFPD_SHIFT 0
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#define VIDTCON0_VFPD_LIMIT 0xffff
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#define VIDTCON0_VFPD(_x) ((_x) << 0)
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/* VIDTCON1 */
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#define VIDTCON1 0x614
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#define VIDTCON1_VSPW_MASK (0xffff << 16)
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#define VIDTCON1_VSPW_SHIFT 16
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#define VIDTCON1_VSPW_LIMIT 0xffff
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#define VIDTCON1_VSPW(_x) ((_x) << 16)
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/* VIDTCON2 */
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#define VIDTCON2 0x618
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#define VIDTCON2_HBPD_MASK (0xffff << 16)
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#define VIDTCON2_HBPD_SHIFT 16
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#define VIDTCON2_HBPD_LIMIT 0xffff
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#define VIDTCON2_HBPD(_x) ((_x) << 16)
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#define VIDTCON2_HFPD_MASK (0xffff << 0)
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#define VIDTCON2_HFPD_SHIFT 0
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#define VIDTCON2_HFPD_LIMIT 0xffff
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#define VIDTCON2_HFPD(_x) ((_x) << 0)
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/* VIDTCON3 */
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#define VIDTCON3 0x61C
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#define VIDTCON3_HSPW_MASK (0xffff << 16)
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#define VIDTCON3_HSPW_SHIFT 16
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#define VIDTCON3_HSPW_LIMIT 0xffff
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#define VIDTCON3_HSPW(_x) ((_x) << 16)
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/* VIDTCON4 */
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#define VIDTCON4 0x620
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#define VIDTCON4_LINEVAL_MASK (0xfff << 16)
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#define VIDTCON4_LINEVAL_SHIFT 16
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#define VIDTCON4_LINEVAL_LIMIT 0xfff
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#define VIDTCON4_LINEVAL(_x) (((_x) & 0xfff) << 16)
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#define VIDTCON4_HOZVAL_MASK (0xfff << 0)
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#define VIDTCON4_HOZVAL_SHIFT 0
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#define VIDTCON4_HOZVAL_LIMIT 0xfff
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#define VIDTCON4_HOZVAL(_x) (((_x) & 0xfff) << 0)
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/* LINECNT OP THRSHOLD*/
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#define LINECNT_OP_THRESHOLD 0x630
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/* CRCCTRL */
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#define CRCCTRL 0x6C8
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#define CRCCTRL_CRCCLKEN (0x1 << 2)
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#define CRCCTRL_CRCSTART_F (0x1 << 1)
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#define CRCCTRL_CRCEN (0x1 << 0)
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/* DECON_CMU */
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#define DECON_CMU 0x704
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#define DECON_CMU_ALL_CLKGATE_ENABLE 0x3
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#define DECON_CMU_SE_CLKGATE_ENABLE (0x1 << 2)
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#define DECON_CMU_SFR_CLKGATE_ENABLE (0x1 << 1)
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#define DECON_CMU_MEM_CLKGATE_ENABLE (0x1 << 0)
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/* DECON_UPDATE */
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#define DECON_UPDATE 0x710
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#define DECON_UPDATE_SLAVE_SYNC (1 << 4)
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#define DECON_UPDATE_STANDALONE_F (1 << 0)
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#endif /* EXYNOS_REGS_DECON7_H */
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