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0d5204abe5
Add clock phandle, of the core clock driving the mdio block, as an optional property to the Broadcom iProc mdio mux. The clock, when specified, will be used to setup the rate adjust registers in the mdio to derrive the mdio's operating frequency. Signed-off-by: Arun Parameswaran <arun.parameswaran@broadcom.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net>
63 lines
1.5 KiB
Plaintext
63 lines
1.5 KiB
Plaintext
Properties for an MDIO bus multiplexer found in Broadcom iProc based SoCs.
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This MDIO bus multiplexer defines buses that could be internal as well as
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external to SoCs and could accept MDIO transaction compatible to C-22 or
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C-45 Clause. When child bus is selected, one needs to select these two
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properties as well to generate desired MDIO transaction on appropriate bus.
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Required properties in addition to the generic multiplexer properties:
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MDIO multiplexer node:
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- compatible: brcm,mdio-mux-iproc.
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Every non-ethernet PHY requires a compatible so that it could be probed based
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on this compatible string.
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Optional properties:
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- clocks: phandle of the core clock which drives the mdio block.
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Additional information regarding generic multiplexer properties can be found
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at- Documentation/devicetree/bindings/net/mdio-mux.txt
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for example:
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mdio_mux_iproc: mdio-mux@66020000 {
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compatible = "brcm,mdio-mux-iproc";
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reg = <0x66020000 0x250>;
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#address-cells = <1>;
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#size-cells = <0>;
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mdio@0 {
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reg = <0x0>;
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#address-cells = <1>;
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#size-cells = <0>;
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pci_phy0: pci-phy@0 {
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compatible = "brcm,ns2-pcie-phy";
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reg = <0x0>;
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#phy-cells = <0>;
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};
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};
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mdio@7 {
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reg = <0x7>;
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#address-cells = <1>;
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#size-cells = <0>;
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pci_phy1: pci-phy@0 {
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compatible = "brcm,ns2-pcie-phy";
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reg = <0x0>;
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#phy-cells = <0>;
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};
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};
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mdio@10 {
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reg = <0x10>;
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#address-cells = <1>;
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#size-cells = <0>;
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gphy0: eth-phy@10 {
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reg = <0x10>;
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};
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};
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};
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