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00b4c90787
ARMv6K CPUs have SEV (send event) and WFE (wait for event) instructions which allow the CPU clock to be suspended until another CPU issues a SEV, rather than spinning on the lock wasting power. Make use of these instructions. Note that WFE does not wait if an event has been sent since the last WFE cleared the event status, so although it may look racy, the instruction implementation ensures that these are dealt with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
202 lines
3.7 KiB
C
202 lines
3.7 KiB
C
#ifndef __ASM_SPINLOCK_H
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#define __ASM_SPINLOCK_H
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#if __LINUX_ARM_ARCH__ < 6
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#error SMP not supported on pre-ARMv6 CPUs
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#endif
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/*
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* ARMv6 Spin-locking.
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*
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* We exclusively read the old value. If it is zero, we may have
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* won the lock, so we try exclusively storing it. A memory barrier
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* is required after we get a lock, and before we release it, because
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* V6 CPUs are assumed to have weakly ordered memory.
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*
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* Unlocked value: 0
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* Locked value: 1
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*/
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#define __raw_spin_is_locked(x) ((x)->lock != 0)
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#define __raw_spin_unlock_wait(lock) \
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do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
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#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
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static inline void __raw_spin_lock(raw_spinlock_t *lock)
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{
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unsigned long tmp;
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__asm__ __volatile__(
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"1: ldrex %0, [%1]\n"
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" teq %0, #0\n"
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#ifdef CONFIG_CPU_32v6K
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" wfene\n"
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#endif
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" strexeq %0, %2, [%1]\n"
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" teqeq %0, #0\n"
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" bne 1b"
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: "=&r" (tmp)
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: "r" (&lock->lock), "r" (1)
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: "cc");
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smp_mb();
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}
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static inline int __raw_spin_trylock(raw_spinlock_t *lock)
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{
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unsigned long tmp;
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__asm__ __volatile__(
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" ldrex %0, [%1]\n"
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" teq %0, #0\n"
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" strexeq %0, %2, [%1]"
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: "=&r" (tmp)
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: "r" (&lock->lock), "r" (1)
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: "cc");
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if (tmp == 0) {
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smp_mb();
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return 1;
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} else {
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return 0;
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}
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}
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static inline void __raw_spin_unlock(raw_spinlock_t *lock)
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{
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smp_mb();
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__asm__ __volatile__(
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" str %1, [%0]\n"
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#ifdef CONFIG_CPU_32v6K
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" mcr p15, 0, %1, c7, c10, 4\n" /* DSB */
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" sev"
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#endif
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:
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: "r" (&lock->lock), "r" (0)
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: "cc");
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}
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/*
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* RWLOCKS
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*
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*
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* Write locks are easy - we just set bit 31. When unlocking, we can
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* just write zero since the lock is exclusively held.
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*/
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#define rwlock_is_locked(x) (*((volatile unsigned int *)(x)) != 0)
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static inline void __raw_write_lock(raw_rwlock_t *rw)
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{
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unsigned long tmp;
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__asm__ __volatile__(
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"1: ldrex %0, [%1]\n"
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" teq %0, #0\n"
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#ifdef CONFIG_CPU_32v6K
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" wfene\n"
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#endif
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" strexeq %0, %2, [%1]\n"
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" teq %0, #0\n"
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" bne 1b"
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: "=&r" (tmp)
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: "r" (&rw->lock), "r" (0x80000000)
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: "cc");
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smp_mb();
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}
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static inline int __raw_write_trylock(raw_rwlock_t *rw)
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{
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unsigned long tmp;
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__asm__ __volatile__(
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"1: ldrex %0, [%1]\n"
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" teq %0, #0\n"
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" strexeq %0, %2, [%1]"
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: "=&r" (tmp)
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: "r" (&rw->lock), "r" (0x80000000)
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: "cc");
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if (tmp == 0) {
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smp_mb();
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return 1;
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} else {
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return 0;
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}
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}
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static inline void __raw_write_unlock(raw_rwlock_t *rw)
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{
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smp_mb();
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__asm__ __volatile__(
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"str %1, [%0]\n"
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#ifdef CONFIG_CPU_32v6K
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" mcr p15, 0, %1, c7, c10, 4\n" /* DSB */
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" sev\n"
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#endif
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:
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: "r" (&rw->lock), "r" (0)
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: "cc");
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}
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/*
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* Read locks are a bit more hairy:
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* - Exclusively load the lock value.
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* - Increment it.
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* - Store new lock value if positive, and we still own this location.
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* If the value is negative, we've already failed.
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* - If we failed to store the value, we want a negative result.
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* - If we failed, try again.
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* Unlocking is similarly hairy. We may have multiple read locks
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* currently active. However, we know we won't have any write
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* locks.
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*/
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static inline void __raw_read_lock(raw_rwlock_t *rw)
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{
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unsigned long tmp, tmp2;
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__asm__ __volatile__(
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"1: ldrex %0, [%2]\n"
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" adds %0, %0, #1\n"
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" strexpl %1, %0, [%2]\n"
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#ifdef CONFIG_CPU_32v6K
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" wfemi\n"
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#endif
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" rsbpls %0, %1, #0\n"
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" bmi 1b"
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: "=&r" (tmp), "=&r" (tmp2)
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: "r" (&rw->lock)
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: "cc");
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smp_mb();
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}
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static inline void __raw_read_unlock(raw_rwlock_t *rw)
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{
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unsigned long tmp, tmp2;
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smp_mb();
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__asm__ __volatile__(
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"1: ldrex %0, [%2]\n"
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" sub %0, %0, #1\n"
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" strex %1, %0, [%2]\n"
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" teq %1, #0\n"
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" bne 1b"
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#ifdef CONFIG_CPU_32v6K
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"\n cmp %0, #0\n"
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" mcreq p15, 0, %0, c7, c10, 4\n"
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" seveq"
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#endif
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: "=&r" (tmp), "=&r" (tmp2)
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: "r" (&rw->lock)
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: "cc");
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}
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#define __raw_read_trylock(lock) generic__raw_read_trylock(lock)
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#endif /* __ASM_SPINLOCK_H */
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