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f658f21c65
Geert writes:
Summary:
- Clean up the naming of clocks in the sh-sci driver and its DT bindings,
- Add support for the optional external clock on (H)SCI(F), where this pin
can serve as a clock input,
- Add support for the optional clock sources for the Baud Rate
Generator for External Clock (BRG), as found on some SCIF variants
and on HSCIF.
94 lines
4.8 KiB
Plaintext
94 lines
4.8 KiB
Plaintext
* Renesas SH-Mobile Serial Communication Interface
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Required properties:
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- compatible: Must contain one or more of the following:
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- "renesas,scif-r7s72100" for R7S72100 (RZ/A1H) SCIF compatible UART.
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- "renesas,scifa-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFA compatible UART.
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- "renesas,scifb-r8a73a4" for R8A73A4 (R-Mobile APE6) SCIFB compatible UART.
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- "renesas,scifa-r8a7740" for R8A7740 (R-Mobile A1) SCIFA compatible UART.
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- "renesas,scifb-r8a7740" for R8A7740 (R-Mobile A1) SCIFB compatible UART.
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- "renesas,scif-r8a7778" for R8A7778 (R-Car M1) SCIF compatible UART.
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- "renesas,scif-r8a7779" for R8A7779 (R-Car H1) SCIF compatible UART.
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- "renesas,scif-r8a7790" for R8A7790 (R-Car H2) SCIF compatible UART.
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- "renesas,scifa-r8a7790" for R8A7790 (R-Car H2) SCIFA compatible UART.
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- "renesas,scifb-r8a7790" for R8A7790 (R-Car H2) SCIFB compatible UART.
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- "renesas,hscif-r8a7790" for R8A7790 (R-Car H2) HSCIF compatible UART.
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- "renesas,scif-r8a7791" for R8A7791 (R-Car M2-W) SCIF compatible UART.
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- "renesas,scifa-r8a7791" for R8A7791 (R-Car M2-W) SCIFA compatible UART.
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- "renesas,scifb-r8a7791" for R8A7791 (R-Car M2-W) SCIFB compatible UART.
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- "renesas,hscif-r8a7791" for R8A7791 (R-Car M2-W) HSCIF compatible UART.
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- "renesas,scif-r8a7793" for R8A7793 (R-Car M2-N) SCIF compatible UART.
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- "renesas,scifa-r8a7793" for R8A7793 (R-Car M2-N) SCIFA compatible UART.
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- "renesas,scifb-r8a7793" for R8A7793 (R-Car M2-N) SCIFB compatible UART.
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- "renesas,hscif-r8a7793" for R8A7793 (R-Car M2-N) HSCIF compatible UART.
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- "renesas,scif-r8a7794" for R8A7794 (R-Car E2) SCIF compatible UART.
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- "renesas,scifa-r8a7794" for R8A7794 (R-Car E2) SCIFA compatible UART.
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- "renesas,scifb-r8a7794" for R8A7794 (R-Car E2) SCIFB compatible UART.
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- "renesas,hscif-r8a7794" for R8A7794 (R-Car E2) HSCIF compatible UART.
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- "renesas,scif-r8a7795" for R8A7795 (R-Car H3) SCIF compatible UART.
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- "renesas,hscif-r8a7795" for R8A7795 (R-Car H3) HSCIF compatible UART.
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- "renesas,scifa-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFA compatible UART.
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- "renesas,scifb-sh73a0" for SH73A0 (SH-Mobile AG5) SCIFB compatible UART.
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- "renesas,rcar-gen1-scif" for R-Car Gen1 SCIF compatible UART,
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- "renesas,rcar-gen2-scif" for R-Car Gen2 SCIF compatible UART,
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- "renesas,rcar-gen3-scif" for R-Car Gen3 SCIF compatible UART,
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- "renesas,rcar-gen2-scifa" for R-Car Gen2 SCIFA compatible UART,
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- "renesas,rcar-gen2-scifb" for R-Car Gen2 SCIFB compatible UART,
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- "renesas,rcar-gen1-hscif" for R-Car Gen1 HSCIF compatible UART,
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- "renesas,rcar-gen2-hscif" for R-Car Gen2 HSCIF compatible UART,
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- "renesas,rcar-gen3-hscif" for R-Car Gen3 HSCIF compatible UART,
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- "renesas,scif" for generic SCIF compatible UART.
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- "renesas,scifa" for generic SCIFA compatible UART.
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- "renesas,scifb" for generic SCIFB compatible UART.
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- "renesas,hscif" for generic HSCIF compatible UART.
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- "renesas,sci" for generic SCI compatible UART.
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When compatible with the generic version, nodes must list the
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SoC-specific version corresponding to the platform first, followed by the
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family-specific and/or generic versions.
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- reg: Base address and length of the I/O registers used by the UART.
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- interrupts: Must contain an interrupt-specifier for the SCIx interrupt.
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- clocks: Must contain a phandle and clock-specifier pair for each entry
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in clock-names.
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- clock-names: Must contain "fck" for the SCIx UART functional clock.
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Apart from the divided functional clock, there may be other possible
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sources for the sampling clock, depending on SCIx variant.
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On (H)SCI(F) and some SCIFA, an additional clock may be specified:
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- "hsck" for the optional external clock input (on HSCIF),
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- "sck" for the optional external clock input (on other variants).
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On UARTs equipped with a Baud Rate Generator for External Clock (BRG)
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(some SCIF and HSCIF), additional clocks may be specified:
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- "brg_int" for the optional internal clock source for the frequency
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divider (typically the (AXI or SHwy) bus clock),
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- "scif_clk" for the optional external clock source for the frequency
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divider (SCIF_CLK).
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Note: Each enabled SCIx UART should have an alias correctly numbered in the
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"aliases" node.
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Optional properties:
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- dmas: Must contain a list of two references to DMA specifiers, one for
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transmission, and one for reception.
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- dma-names: Must contain a list of two DMA names, "tx" and "rx".
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Example:
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aliases {
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serial0 = &scifa0;
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};
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scifa0: serial@e6c40000 {
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compatible = "renesas,scifa-r8a7790",
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"renesas,rcar-gen2-scifa", "renesas,scifa";
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reg = <0 0xe6c40000 0 64>;
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interrupt-parent = <&gic>;
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interrupts = <0 144 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp2_clks R8A7790_CLK_SCIFA0>;
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clock-names = "fck";
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dmas = <&dmac0 0x21>, <&dmac0 0x22>;
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dma-names = "tx", "rx";
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};
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