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bf81e2f100
spll_gate was added with commit b7eed20761
"ARM: imx27: add a clock gate to activate SPLL clock".
spll_gate is missing in the devicetree clock documentation for imx27. This
patch adds it to the list of clocks in the documentation.
Signed-off-by: Markus Pargmann <mpa@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
119 lines
2.8 KiB
Plaintext
119 lines
2.8 KiB
Plaintext
* Clock bindings for Freescale i.MX27
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Required properties:
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- compatible: Should be "fsl,imx27-ccm"
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- reg: Address and length of the register set
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- interrupts: Should contain CCM interrupt
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- #clock-cells: Should be <1>
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The clock consumer should specify the desired clock by having the clock
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ID in its "clocks" phandle cell. The following is a full list of i.MX27
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clocks and IDs.
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Clock ID
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-----------------------
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dummy 0
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ckih 1
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ckil 2
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mpll 3
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spll 4
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mpll_main2 5
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ahb 6
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ipg 7
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nfc_div 8
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per1_div 9
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per2_div 10
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per3_div 11
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per4_div 12
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vpu_sel 13
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vpu_div 14
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usb_div 15
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cpu_sel 16
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clko_sel 17
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cpu_div 18
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clko_div 19
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ssi1_sel 20
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ssi2_sel 21
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ssi1_div 22
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ssi2_div 23
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clko_en 24
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ssi2_ipg_gate 25
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ssi1_ipg_gate 26
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slcdc_ipg_gate 27
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sdhc3_ipg_gate 28
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sdhc2_ipg_gate 29
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sdhc1_ipg_gate 30
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scc_ipg_gate 31
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sahara_ipg_gate 32
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rtc_ipg_gate 33
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pwm_ipg_gate 34
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owire_ipg_gate 35
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lcdc_ipg_gate 36
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kpp_ipg_gate 37
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iim_ipg_gate 38
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i2c2_ipg_gate 39
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i2c1_ipg_gate 40
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gpt6_ipg_gate 41
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gpt5_ipg_gate 42
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gpt4_ipg_gate 43
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gpt3_ipg_gate 44
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gpt2_ipg_gate 45
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gpt1_ipg_gate 46
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gpio_ipg_gate 47
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fec_ipg_gate 48
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emma_ipg_gate 49
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dma_ipg_gate 50
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cspi3_ipg_gate 51
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cspi2_ipg_gate 52
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cspi1_ipg_gate 53
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nfc_baud_gate 54
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ssi2_baud_gate 55
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ssi1_baud_gate 56
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vpu_baud_gate 57
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per4_gate 58
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per3_gate 59
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per2_gate 60
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per1_gate 61
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usb_ahb_gate 62
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slcdc_ahb_gate 63
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sahara_ahb_gate 64
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lcdc_ahb_gate 65
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vpu_ahb_gate 66
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fec_ahb_gate 67
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emma_ahb_gate 68
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emi_ahb_gate 69
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dma_ahb_gate 70
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csi_ahb_gate 71
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brom_ahb_gate 72
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ata_ahb_gate 73
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wdog_ipg_gate 74
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usb_ipg_gate 75
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uart6_ipg_gate 76
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uart5_ipg_gate 77
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uart4_ipg_gate 78
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uart3_ipg_gate 79
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uart2_ipg_gate 80
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uart1_ipg_gate 81
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ckih_div1p5 82
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fpm 83
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mpll_osc_sel 84
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mpll_sel 85
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spll_gate 86
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Examples:
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clks: ccm@10027000{
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compatible = "fsl,imx27-ccm";
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reg = <0x10027000 0x1000>;
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#clock-cells = <1>;
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};
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uart1: serial@1000a000 {
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compatible = "fsl,imx27-uart", "fsl,imx21-uart";
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reg = <0x1000a000 0x1000>;
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interrupts = <20>;
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clocks = <&clks 81>, <&clks 61>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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