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93c0eac40d
Let's support __HAVE_ARCH_PTE_SWP_EXCLUSIVE just like we already do on x86-64. After deciphering the PTE layout it becomes clear that there are still unused bits for 2-level and 3-level page tables that we should be able to use. Reusing a bit avoids stealing one bit from the swap offset. While at it, mask the type in __swp_entry(); use some helper definitions to make the macros easier to grasp. Link: https://lkml.kernel.org/r/20230113171026.582290-25-david@redhat.com Signed-off-by: David Hildenbrand <david@redhat.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Ingo Molnar <mingo@redhat.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: "H. Peter Anvin" <hpa@zytor.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
210 lines
6.5 KiB
C
210 lines
6.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_X86_PGTABLE_3LEVEL_H
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#define _ASM_X86_PGTABLE_3LEVEL_H
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/*
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* Intel Physical Address Extension (PAE) Mode - three-level page
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* tables on PPro+ CPUs.
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*
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* Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
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*/
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#define pte_ERROR(e) \
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pr_err("%s:%d: bad pte %p(%08lx%08lx)\n", \
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__FILE__, __LINE__, &(e), (e).pte_high, (e).pte_low)
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#define pmd_ERROR(e) \
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pr_err("%s:%d: bad pmd %p(%016Lx)\n", \
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__FILE__, __LINE__, &(e), pmd_val(e))
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#define pgd_ERROR(e) \
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pr_err("%s:%d: bad pgd %p(%016Lx)\n", \
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__FILE__, __LINE__, &(e), pgd_val(e))
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#define pxx_xchg64(_pxx, _ptr, _val) ({ \
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_pxx##val_t *_p = (_pxx##val_t *)_ptr; \
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_pxx##val_t _o = *_p; \
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do { } while (!try_cmpxchg64(_p, &_o, (_val))); \
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native_make_##_pxx(_o); \
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})
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/*
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* Rules for using set_pte: the pte being assigned *must* be
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* either not present or in a state where the hardware will
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* not attempt to update the pte. In places where this is
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* not possible, use pte_get_and_clear to obtain the old pte
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* value and then use set_pte to update it. -ben
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*/
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static inline void native_set_pte(pte_t *ptep, pte_t pte)
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{
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WRITE_ONCE(ptep->pte_high, pte.pte_high);
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smp_wmb();
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WRITE_ONCE(ptep->pte_low, pte.pte_low);
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}
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static inline void native_set_pte_atomic(pte_t *ptep, pte_t pte)
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{
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pxx_xchg64(pte, ptep, native_pte_val(pte));
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}
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static inline void native_set_pmd(pmd_t *pmdp, pmd_t pmd)
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{
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pxx_xchg64(pmd, pmdp, native_pmd_val(pmd));
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}
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static inline void native_set_pud(pud_t *pudp, pud_t pud)
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{
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#ifdef CONFIG_PAGE_TABLE_ISOLATION
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pud.p4d.pgd = pti_set_user_pgtbl(&pudp->p4d.pgd, pud.p4d.pgd);
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#endif
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pxx_xchg64(pud, pudp, native_pud_val(pud));
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}
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/*
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* For PTEs and PDEs, we must clear the P-bit first when clearing a page table
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* entry, so clear the bottom half first and enforce ordering with a compiler
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* barrier.
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*/
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static inline void native_pte_clear(struct mm_struct *mm, unsigned long addr,
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pte_t *ptep)
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{
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WRITE_ONCE(ptep->pte_low, 0);
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smp_wmb();
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WRITE_ONCE(ptep->pte_high, 0);
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}
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static inline void native_pmd_clear(pmd_t *pmdp)
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{
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WRITE_ONCE(pmdp->pmd_low, 0);
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smp_wmb();
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WRITE_ONCE(pmdp->pmd_high, 0);
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}
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static inline void native_pud_clear(pud_t *pudp)
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{
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}
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static inline void pud_clear(pud_t *pudp)
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{
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set_pud(pudp, __pud(0));
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/*
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* According to Intel App note "TLBs, Paging-Structure Caches,
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* and Their Invalidation", April 2007, document 317080-001,
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* section 8.1: in PAE mode we explicitly have to flush the
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* TLB via cr3 if the top-level pgd is changed...
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*
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* Currently all places where pud_clear() is called either have
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* flush_tlb_mm() followed or don't need TLB flush (x86_64 code or
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* pud_clear_bad()), so we don't need TLB flush here.
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*/
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}
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#ifdef CONFIG_SMP
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static inline pte_t native_ptep_get_and_clear(pte_t *ptep)
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{
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return pxx_xchg64(pte, ptep, 0ULL);
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}
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static inline pmd_t native_pmdp_get_and_clear(pmd_t *pmdp)
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{
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return pxx_xchg64(pmd, pmdp, 0ULL);
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}
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static inline pud_t native_pudp_get_and_clear(pud_t *pudp)
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{
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return pxx_xchg64(pud, pudp, 0ULL);
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}
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#else
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#define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp)
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#define native_pmdp_get_and_clear(xp) native_local_pmdp_get_and_clear(xp)
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#define native_pudp_get_and_clear(xp) native_local_pudp_get_and_clear(xp)
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#endif
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#ifndef pmdp_establish
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#define pmdp_establish pmdp_establish
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static inline pmd_t pmdp_establish(struct vm_area_struct *vma,
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unsigned long address, pmd_t *pmdp, pmd_t pmd)
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{
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pmd_t old;
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/*
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* If pmd has present bit cleared we can get away without expensive
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* cmpxchg64: we can update pmdp half-by-half without racing with
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* anybody.
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*/
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if (!(pmd_val(pmd) & _PAGE_PRESENT)) {
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/* xchg acts as a barrier before setting of the high bits */
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old.pmd_low = xchg(&pmdp->pmd_low, pmd.pmd_low);
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old.pmd_high = READ_ONCE(pmdp->pmd_high);
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WRITE_ONCE(pmdp->pmd_high, pmd.pmd_high);
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return old;
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}
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return pxx_xchg64(pmd, pmdp, pmd.pmd);
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}
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#endif
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/*
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* Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
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* are !pte_none() && !pte_present().
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*
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* Format of swap PTEs:
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*
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* 6 6 6 6 5 5 5 5 5 5 5 5 5 5 4 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3
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* 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
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* < type -> <---------------------- offset ----------------------
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*
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* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* --------------------------------------------> 0 E 0 0 0 0 0 0 0
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*
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* E is the exclusive marker that is not stored in swap entries.
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*/
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#define SWP_TYPE_BITS 5
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#define _SWP_TYPE_MASK ((1U << SWP_TYPE_BITS) - 1)
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#define SWP_OFFSET_FIRST_BIT (_PAGE_BIT_PROTNONE + 1)
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/* We always extract/encode the offset by shifting it all the way up, and then down again */
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#define SWP_OFFSET_SHIFT (SWP_OFFSET_FIRST_BIT + SWP_TYPE_BITS)
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#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > SWP_TYPE_BITS)
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#define __swp_type(x) (((x).val) & _SWP_TYPE_MASK)
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#define __swp_offset(x) ((x).val >> SWP_TYPE_BITS)
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#define __swp_entry(type, offset) ((swp_entry_t){((type) & _SWP_TYPE_MASK) \
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| (offset) << SWP_TYPE_BITS})
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/*
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* Normally, __swp_entry() converts from arch-independent swp_entry_t to
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* arch-dependent swp_entry_t, and __swp_entry_to_pte() just stores the result
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* to pte. But here we have 32bit swp_entry_t and 64bit pte, and need to use the
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* whole 64 bits. Thus, we shift the "real" arch-dependent conversion to
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* __swp_entry_to_pte() through the following helper macro based on 64bit
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* __swp_entry().
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*/
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#define __swp_pteval_entry(type, offset) ((pteval_t) { \
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(~(pteval_t)(offset) << SWP_OFFSET_SHIFT >> SWP_TYPE_BITS) \
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| ((pteval_t)(type) << (64 - SWP_TYPE_BITS)) })
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#define __swp_entry_to_pte(x) ((pte_t){ .pte = \
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__swp_pteval_entry(__swp_type(x), __swp_offset(x)) })
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/*
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* Analogically, __pte_to_swp_entry() doesn't just extract the arch-dependent
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* swp_entry_t, but also has to convert it from 64bit to the 32bit
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* intermediate representation, using the following macros based on 64bit
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* __swp_type() and __swp_offset().
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*/
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#define __pteval_swp_type(x) ((unsigned long)((x).pte >> (64 - SWP_TYPE_BITS)))
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#define __pteval_swp_offset(x) ((unsigned long)(~((x).pte) << SWP_TYPE_BITS >> SWP_OFFSET_SHIFT))
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#define __pte_to_swp_entry(pte) (__swp_entry(__pteval_swp_type(pte), \
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__pteval_swp_offset(pte)))
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/* We borrow bit 7 to store the exclusive marker in swap PTEs. */
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#define _PAGE_SWP_EXCLUSIVE _PAGE_PSE
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#include <asm/pgtable-invert.h>
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#endif /* _ASM_X86_PGTABLE_3LEVEL_H */
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