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Add bindings documentation for i.MX7 media drivers. The imx7 MIPI CSI2 and imx7 CMOS Sensor Interface. Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl> Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
91 lines
3.4 KiB
Plaintext
91 lines
3.4 KiB
Plaintext
Freescale i.MX7 Mipi CSI2
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=========================
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mipi_csi2 node
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--------------
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This is the device node for the MIPI CSI-2 receiver core in i.MX7 SoC. It is
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compatible with previous version of Samsung D-phy.
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Required properties:
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- compatible : "fsl,imx7-mipi-csi2";
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- reg : base address and length of the register set for the device;
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- interrupts : should contain MIPI CSIS interrupt;
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- clocks : list of clock specifiers, see
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Documentation/devicetree/bindings/clock/clock-bindings.txt for details;
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- clock-names : must contain "pclk", "wrap" and "phy" entries, matching
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entries in the clock property;
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- power-domains : a phandle to the power domain, see
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Documentation/devicetree/bindings/power/power_domain.txt for details.
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- reset-names : should include following entry "mrst";
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- resets : a list of phandle, should contain reset entry of
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reset-names;
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- phy-supply : from the generic phy bindings, a phandle to a regulator that
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provides power to MIPI CSIS core;
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Optional properties:
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- clock-frequency : The IP's main (system bus) clock frequency in Hz, default
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value when this property is not specified is 166 MHz;
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- fsl,csis-hs-settle : differential receiver (HS-RX) settle time;
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The device node should contain two 'port' child nodes with one child 'endpoint'
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node, according to the bindings defined in:
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Documentation/devicetree/bindings/ media/video-interfaces.txt.
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The following are properties specific to those nodes.
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port node
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---------
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- reg : (required) can take the values 0 or 1, where 0 shall be
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related to the sink port and port 1 shall be the source
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one;
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endpoint node
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-------------
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- data-lanes : (required) an array specifying active physical MIPI-CSI2
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data input lanes and their mapping to logical lanes; this
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shall only be applied to port 0 (sink port), the array's
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content is unused only its length is meaningful,
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in this case the maximum length supported is 2;
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example:
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mipi_csi: mipi-csi@30750000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx7-mipi-csi2";
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reg = <0x30750000 0x10000>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX7D_IPG_ROOT_CLK>,
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<&clks IMX7D_MIPI_CSI_ROOT_CLK>,
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<&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
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clock-names = "pclk", "wrap", "phy";
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clock-frequency = <166000000>;
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power-domains = <&pgc_mipi_phy>;
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phy-supply = <®_1p0d>;
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resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
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reset-names = "mrst";
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fsl,csis-hs-settle = <3>;
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port@0 {
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reg = <0>;
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mipi_from_sensor: endpoint {
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remote-endpoint = <&ov2680_to_mipi>;
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data-lanes = <1>;
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};
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};
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port@1 {
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reg = <1>;
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mipi_vc0_to_csi_mux: endpoint {
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remote-endpoint = <&csi_mux_from_mipi_vc0>;
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};
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};
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};
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