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5402626c83
Add driver for HDMI output. HDMI PHY registers are mixed into HDMI device registers and their is only one IRQ for all this hardware block. That is why PHYs aren't using phy framework but only a thin hdmi_phy_ops structure with start and stop functions. HDMI driver is mapped on drm_bridge and drm_connector structures. Signed-off-by: Benjamin Gaignard <benjamin.gaignard@linaro.org> Reviewed-by: Rob Clark <robdclark@gmail.com>
337 lines
10 KiB
C
337 lines
10 KiB
C
/*
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* Copyright (C) STMicroelectronics SA 2014
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* Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics.
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* License terms: GNU General Public License (GPL), version 2
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*/
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#include "sti_hdmi_tx3g0c55phy.h"
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#define HDMI_SRZ_PLL_CFG 0x0504
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#define HDMI_SRZ_TAP_1 0x0508
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#define HDMI_SRZ_TAP_2 0x050C
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#define HDMI_SRZ_TAP_3 0x0510
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#define HDMI_SRZ_CTRL 0x0514
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#define HDMI_SRZ_PLL_CFG_POWER_DOWN BIT(0)
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#define HDMI_SRZ_PLL_CFG_VCOR_SHIFT 1
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#define HDMI_SRZ_PLL_CFG_VCOR_425MHZ 0
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#define HDMI_SRZ_PLL_CFG_VCOR_850MHZ 1
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#define HDMI_SRZ_PLL_CFG_VCOR_1700MHZ 2
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#define HDMI_SRZ_PLL_CFG_VCOR_3000MHZ 3
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#define HDMI_SRZ_PLL_CFG_VCOR_MASK 3
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#define HDMI_SRZ_PLL_CFG_VCOR(x) (x << HDMI_SRZ_PLL_CFG_VCOR_SHIFT)
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#define HDMI_SRZ_PLL_CFG_NDIV_SHIFT 8
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#define HDMI_SRZ_PLL_CFG_NDIV_MASK (0x1F << HDMI_SRZ_PLL_CFG_NDIV_SHIFT)
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#define HDMI_SRZ_PLL_CFG_MODE_SHIFT 16
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#define HDMI_SRZ_PLL_CFG_MODE_13_5_MHZ 0x1
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#define HDMI_SRZ_PLL_CFG_MODE_25_2_MHZ 0x4
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#define HDMI_SRZ_PLL_CFG_MODE_27_MHZ 0x5
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#define HDMI_SRZ_PLL_CFG_MODE_33_75_MHZ 0x6
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#define HDMI_SRZ_PLL_CFG_MODE_40_5_MHZ 0x7
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#define HDMI_SRZ_PLL_CFG_MODE_54_MHZ 0x8
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#define HDMI_SRZ_PLL_CFG_MODE_67_5_MHZ 0x9
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#define HDMI_SRZ_PLL_CFG_MODE_74_25_MHZ 0xA
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#define HDMI_SRZ_PLL_CFG_MODE_81_MHZ 0xB
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#define HDMI_SRZ_PLL_CFG_MODE_82_5_MHZ 0xC
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#define HDMI_SRZ_PLL_CFG_MODE_108_MHZ 0xD
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#define HDMI_SRZ_PLL_CFG_MODE_148_5_MHZ 0xE
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#define HDMI_SRZ_PLL_CFG_MODE_165_MHZ 0xF
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#define HDMI_SRZ_PLL_CFG_MODE_MASK 0xF
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#define HDMI_SRZ_PLL_CFG_MODE(x) (x << HDMI_SRZ_PLL_CFG_MODE_SHIFT)
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#define HDMI_SRZ_CTRL_POWER_DOWN (1 << 0)
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#define HDMI_SRZ_CTRL_EXTERNAL_DATA_EN (1 << 1)
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/* sysconf registers */
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#define HDMI_REJECTION_PLL_CONFIGURATION 0x0858 /* SYSTEM_CONFIG2534 */
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#define HDMI_REJECTION_PLL_STATUS 0x0948 /* SYSTEM_CONFIG2594 */
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#define REJECTION_PLL_HDMI_ENABLE_SHIFT 0
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#define REJECTION_PLL_HDMI_ENABLE_MASK (0x1 << REJECTION_PLL_HDMI_ENABLE_SHIFT)
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#define REJECTION_PLL_HDMI_PDIV_SHIFT 24
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#define REJECTION_PLL_HDMI_PDIV_MASK (0x7 << REJECTION_PLL_HDMI_PDIV_SHIFT)
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#define REJECTION_PLL_HDMI_NDIV_SHIFT 16
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#define REJECTION_PLL_HDMI_NDIV_MASK (0xFF << REJECTION_PLL_HDMI_NDIV_SHIFT)
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#define REJECTION_PLL_HDMI_MDIV_SHIFT 8
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#define REJECTION_PLL_HDMI_MDIV_MASK (0xFF << REJECTION_PLL_HDMI_MDIV_SHIFT)
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#define REJECTION_PLL_HDMI_REJ_PLL_LOCK BIT(0)
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#define HDMI_TIMEOUT_PLL_LOCK 50 /*milliseconds */
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/**
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* pll mode structure
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*
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* A pointer to an array of these structures is passed to a TMDS (HDMI) output
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* via the control interface to provide board and SoC specific
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* configurations of the HDMI PHY. Each entry in the array specifies a hardware
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* specific configuration for a given TMDS clock frequency range. The array
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* should be terminated with an entry that has all fields set to zero.
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*
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* @min: Lower bound of TMDS clock frequency this entry applies to
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* @max: Upper bound of TMDS clock frequency this entry applies to
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* @mode: SoC specific register configuration
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*/
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struct pllmode {
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u32 min;
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u32 max;
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u32 mode;
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};
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#define NB_PLL_MODE 7
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static struct pllmode pllmodes[NB_PLL_MODE] = {
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{13500000, 13513500, HDMI_SRZ_PLL_CFG_MODE_13_5_MHZ},
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{25174800, 25200000, HDMI_SRZ_PLL_CFG_MODE_25_2_MHZ},
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{27000000, 27027000, HDMI_SRZ_PLL_CFG_MODE_27_MHZ},
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{54000000, 54054000, HDMI_SRZ_PLL_CFG_MODE_54_MHZ},
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{72000000, 74250000, HDMI_SRZ_PLL_CFG_MODE_74_25_MHZ},
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{108000000, 108108000, HDMI_SRZ_PLL_CFG_MODE_108_MHZ},
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{148351648, 297000000, HDMI_SRZ_PLL_CFG_MODE_148_5_MHZ}
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};
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#define NB_HDMI_PHY_CONFIG 5
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static struct hdmi_phy_config hdmiphy_config[NB_HDMI_PHY_CONFIG] = {
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{0, 40000000, {0x00101010, 0x00101010, 0x00101010, 0x02} },
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{40000000, 140000000, {0x00111111, 0x00111111, 0x00111111, 0x02} },
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{140000000, 160000000, {0x00131313, 0x00101010, 0x00101010, 0x02} },
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{160000000, 250000000, {0x00131313, 0x00111111, 0x00111111, 0x03FE} },
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{250000000, 300000000, {0x00151515, 0x00101010, 0x00101010, 0x03FE} },
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};
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#define PLL_CHANGE_DELAY 1 /* ms */
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/**
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* Disable the pll rejection
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*
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* @hdmi: pointer on the hdmi internal structure
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*
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* return true if the pll has been disabled
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*/
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static bool disable_pll_rejection(struct sti_hdmi *hdmi)
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{
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u32 val;
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DRM_DEBUG_DRIVER("\n");
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val = readl(hdmi->syscfg + HDMI_REJECTION_PLL_CONFIGURATION);
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val &= ~REJECTION_PLL_HDMI_ENABLE_MASK;
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writel(val, hdmi->syscfg + HDMI_REJECTION_PLL_CONFIGURATION);
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msleep(PLL_CHANGE_DELAY);
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val = readl(hdmi->syscfg + HDMI_REJECTION_PLL_STATUS);
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return !(val & REJECTION_PLL_HDMI_REJ_PLL_LOCK);
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}
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/**
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* Enable the old BCH/rejection PLL is now reused to provide the CLKPXPLL
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* clock input to the new PHY PLL that generates the serializer clock
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* (TMDS*10) and the TMDS clock which is now fed back into the HDMI
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* formatter instead of the TMDS clock line from ClockGenB.
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*
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* @hdmi: pointer on the hdmi internal structure
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*
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* return true if pll has been correctly set
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*/
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static bool enable_pll_rejection(struct sti_hdmi *hdmi)
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{
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unsigned int inputclock;
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u32 mdiv, ndiv, pdiv, val;
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DRM_DEBUG_DRIVER("\n");
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if (!disable_pll_rejection(hdmi))
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return false;
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inputclock = hdmi->mode.clock * 1000;
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DRM_DEBUG_DRIVER("hdmi rejection pll input clock = %dHz\n", inputclock);
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/* Power up the HDMI rejection PLL
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* Note: On this SoC (stiH416) we are forced to have the input clock
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* be equal to the HDMI pixel clock.
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*
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* The values here have been suggested by validation however they are
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* still provisional and subject to change.
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*
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* PLLout = (Fin*Mdiv) / ((2 * Ndiv) / 2^Pdiv)
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*/
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if (inputclock < 50000000) {
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/*
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* For slower clocks we need to multiply more to keep the
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* internal VCO frequency within the physical specification
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* of the PLL.
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*/
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pdiv = 4;
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ndiv = 240;
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mdiv = 30;
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} else {
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pdiv = 2;
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ndiv = 60;
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mdiv = 30;
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}
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val = readl(hdmi->syscfg + HDMI_REJECTION_PLL_CONFIGURATION);
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val &= ~(REJECTION_PLL_HDMI_PDIV_MASK |
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REJECTION_PLL_HDMI_NDIV_MASK |
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REJECTION_PLL_HDMI_MDIV_MASK |
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REJECTION_PLL_HDMI_ENABLE_MASK);
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val |= (pdiv << REJECTION_PLL_HDMI_PDIV_SHIFT) |
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(ndiv << REJECTION_PLL_HDMI_NDIV_SHIFT) |
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(mdiv << REJECTION_PLL_HDMI_MDIV_SHIFT) |
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(0x1 << REJECTION_PLL_HDMI_ENABLE_SHIFT);
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writel(val, hdmi->syscfg + HDMI_REJECTION_PLL_CONFIGURATION);
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msleep(PLL_CHANGE_DELAY);
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val = readl(hdmi->syscfg + HDMI_REJECTION_PLL_STATUS);
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return (val & REJECTION_PLL_HDMI_REJ_PLL_LOCK);
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}
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/**
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* Start hdmi phy macro cell tx3g0c55
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*
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* @hdmi: pointer on the hdmi internal structure
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*
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* Return false if an error occur
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*/
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static bool sti_hdmi_tx3g0c55phy_start(struct sti_hdmi *hdmi)
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{
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u32 ckpxpll = hdmi->mode.clock * 1000;
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u32 val, tmdsck, freqvco, pllctrl = 0;
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unsigned int i;
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if (!enable_pll_rejection(hdmi))
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return false;
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DRM_DEBUG_DRIVER("ckpxpll = %dHz\n", ckpxpll);
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/* Assuming no pixel repetition and 24bits color */
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tmdsck = ckpxpll;
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pllctrl = 2 << HDMI_SRZ_PLL_CFG_NDIV_SHIFT;
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/*
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* Setup the PLL mode parameter based on the ckpxpll. If we haven't got
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* a clock frequency supported by one of the specific PLL modes then we
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* will end up using the generic mode (0) which only supports a 10x
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* multiplier, hence only 24bit color.
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*/
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for (i = 0; i < NB_PLL_MODE; i++) {
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if (ckpxpll >= pllmodes[i].min && ckpxpll <= pllmodes[i].max)
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pllctrl |= HDMI_SRZ_PLL_CFG_MODE(pllmodes[i].mode);
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}
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freqvco = tmdsck * 10;
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if (freqvco <= 425000000UL)
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pllctrl |= HDMI_SRZ_PLL_CFG_VCOR(HDMI_SRZ_PLL_CFG_VCOR_425MHZ);
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else if (freqvco <= 850000000UL)
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pllctrl |= HDMI_SRZ_PLL_CFG_VCOR(HDMI_SRZ_PLL_CFG_VCOR_850MHZ);
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else if (freqvco <= 1700000000UL)
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pllctrl |= HDMI_SRZ_PLL_CFG_VCOR(HDMI_SRZ_PLL_CFG_VCOR_1700MHZ);
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else if (freqvco <= 2970000000UL)
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pllctrl |= HDMI_SRZ_PLL_CFG_VCOR(HDMI_SRZ_PLL_CFG_VCOR_3000MHZ);
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else {
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DRM_ERROR("PHY serializer clock out of range\n");
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goto err;
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}
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/*
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* Configure and power up the PHY PLL
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*/
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hdmi->event_received = false;
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DRM_DEBUG_DRIVER("pllctrl = 0x%x\n", pllctrl);
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hdmi_write(hdmi, pllctrl, HDMI_SRZ_PLL_CFG);
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/* wait PLL interrupt */
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wait_event_interruptible_timeout(hdmi->wait_event,
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hdmi->event_received == true,
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msecs_to_jiffies
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(HDMI_TIMEOUT_PLL_LOCK));
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if ((hdmi_read(hdmi, HDMI_STA) & HDMI_STA_DLL_LCK) == 0) {
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DRM_ERROR("hdmi phy pll not locked\n");
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goto err;
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}
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DRM_DEBUG_DRIVER("got PHY PLL Lock\n");
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/*
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* To configure the source termination and pre-emphasis appropriately
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* for different high speed TMDS clock frequencies a phy configuration
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* table must be provided, tailored to the SoC and board combination.
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*/
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for (i = 0; i < NB_HDMI_PHY_CONFIG; i++) {
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if ((hdmiphy_config[i].min_tmds_freq <= tmdsck) &&
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(hdmiphy_config[i].max_tmds_freq >= tmdsck)) {
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val = hdmiphy_config[i].config[0];
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hdmi_write(hdmi, val, HDMI_SRZ_TAP_1);
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val = hdmiphy_config[i].config[1];
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hdmi_write(hdmi, val, HDMI_SRZ_TAP_2);
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val = hdmiphy_config[i].config[2];
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hdmi_write(hdmi, val, HDMI_SRZ_TAP_3);
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val = hdmiphy_config[i].config[3];
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val |= HDMI_SRZ_CTRL_EXTERNAL_DATA_EN;
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val &= ~HDMI_SRZ_CTRL_POWER_DOWN;
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hdmi_write(hdmi, val, HDMI_SRZ_CTRL);
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DRM_DEBUG_DRIVER("serializer cfg 0x%x 0x%x 0x%x 0x%x\n",
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hdmiphy_config[i].config[0],
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hdmiphy_config[i].config[1],
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hdmiphy_config[i].config[2],
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hdmiphy_config[i].config[3]);
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return true;
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}
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}
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/*
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* Default, power up the serializer with no pre-emphasis or source
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* termination.
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*/
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hdmi_write(hdmi, 0x0, HDMI_SRZ_TAP_1);
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hdmi_write(hdmi, 0x0, HDMI_SRZ_TAP_2);
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hdmi_write(hdmi, 0x0, HDMI_SRZ_TAP_3);
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hdmi_write(hdmi, HDMI_SRZ_CTRL_EXTERNAL_DATA_EN, HDMI_SRZ_CTRL);
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return true;
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err:
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disable_pll_rejection(hdmi);
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return false;
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}
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/**
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* Stop hdmi phy macro cell tx3g0c55
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*
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* @hdmi: pointer on the hdmi internal structure
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*/
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static void sti_hdmi_tx3g0c55phy_stop(struct sti_hdmi *hdmi)
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{
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DRM_DEBUG_DRIVER("\n");
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hdmi->event_received = false;
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hdmi_write(hdmi, HDMI_SRZ_CTRL_POWER_DOWN, HDMI_SRZ_CTRL);
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hdmi_write(hdmi, HDMI_SRZ_PLL_CFG_POWER_DOWN, HDMI_SRZ_PLL_CFG);
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/* wait PLL interrupt */
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wait_event_interruptible_timeout(hdmi->wait_event,
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hdmi->event_received == true,
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msecs_to_jiffies
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(HDMI_TIMEOUT_PLL_LOCK));
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if (hdmi_read(hdmi, HDMI_STA) & HDMI_STA_DLL_LCK)
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DRM_ERROR("hdmi phy pll not well disabled\n");
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disable_pll_rejection(hdmi);
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}
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struct hdmi_phy_ops tx3g0c55phy_ops = {
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.start = sti_hdmi_tx3g0c55phy_start,
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.stop = sti_hdmi_tx3g0c55phy_stop,
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};
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