linux/drivers/gpu
Christian König f5d636d2a7 drm/radeon: use pflip irq on R600+ v2
Testing the update pending bit directly after issuing an
update is nonsense cause depending on the pixel clock the
CRTC needs a bit of time to execute the flip even when we
are in the VBLANK period.

This is just a non invasive patch to solve the problem at
hand, a more complete and cleaner solution should follow
in the next merge window.

Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=76564

v2: fix source IDs for CRTC2-6

Signed-off-by: Christian König <christian.koenig@amd.com>
Cc: stable@vger.kernel.org
2014-05-01 12:27:42 +02:00
..
drm drm/radeon: use pflip irq on R600+ v2 2014-05-01 12:27:42 +02:00
host1x gpu: host1x: handle the correct # of syncpt regs 2014-04-16 17:11:04 +02:00
vga
Makefile