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ac92abcb96
Fixes 85dc74e9 (ARM: dts: omap5 clock data)
On OMAP54xx, For DPLL_IVA, the ref clock(CLKINP) is connected to sys_clk1 and
the bypass input(CLKINPULOW) is connected to iva_dpll_hs_clk_div clock.
But the bypass input is not directly routed to bypass clkout instead
both CLKINP and CLKINPULOW are connected to bypass clkout via a mux.
This mux is controlled by the bit - CM_CLKSEL_DPLL_IVA[23]:DPLL_BYP_CLKSEL
and it's POR value is zero which selects the CLKINP as bypass clkout.
which means iva_dpll_hs_clk_div is not the bypass clock for dpll_iva_ck
Fix this by adding another mux clock as parent in bypass mode.
This design is common to most of the PLLs and the rest have only one bypass
clock. Below is a list of the DPLLs that need this fix:
DPLL_IVA,
DPLL_PER,
DPLL_USB and DPLL_CORE
Signed-off-by: Ravikumar Kattekola <rk@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
1391 lines
30 KiB
Plaintext
1391 lines
30 KiB
Plaintext
/*
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* Device Tree Source for OMAP5 clock data
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*
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* Copyright (C) 2013 Texas Instruments, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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&cm_core_aon_clocks {
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pad_clks_src_ck: pad_clks_src_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <12000000>;
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};
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pad_clks_ck: pad_clks_ck {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&pad_clks_src_ck>;
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ti,bit-shift = <8>;
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reg = <0x0108>;
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};
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secure_32k_clk_src_ck: secure_32k_clk_src_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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slimbus_src_clk: slimbus_src_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <12000000>;
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};
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slimbus_clk: slimbus_clk {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&slimbus_src_clk>;
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ti,bit-shift = <10>;
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reg = <0x0108>;
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};
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sys_32k_ck: sys_32k_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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virt_12000000_ck: virt_12000000_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <12000000>;
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};
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virt_13000000_ck: virt_13000000_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <13000000>;
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};
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virt_16800000_ck: virt_16800000_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <16800000>;
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};
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virt_19200000_ck: virt_19200000_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <19200000>;
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};
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virt_26000000_ck: virt_26000000_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <26000000>;
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};
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virt_27000000_ck: virt_27000000_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <27000000>;
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};
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virt_38400000_ck: virt_38400000_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <38400000>;
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};
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xclk60mhsp1_ck: xclk60mhsp1_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <60000000>;
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};
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xclk60mhsp2_ck: xclk60mhsp2_ck {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <60000000>;
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};
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dpll_abe_ck: dpll_abe_ck {
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#clock-cells = <0>;
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compatible = "ti,omap4-dpll-m4xen-clock";
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clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
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reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
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};
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dpll_abe_x2_ck: dpll_abe_x2_ck {
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#clock-cells = <0>;
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compatible = "ti,omap4-dpll-x2-clock";
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clocks = <&dpll_abe_ck>;
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};
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dpll_abe_m2x2_ck: dpll_abe_m2x2_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_abe_x2_ck>;
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ti,max-div = <31>;
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reg = <0x01f0>;
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ti,index-starts-at-one;
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};
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abe_24m_fclk: abe_24m_fclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_abe_m2x2_ck>;
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clock-mult = <1>;
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clock-div = <8>;
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};
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abe_clk: abe_clk {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_abe_m2x2_ck>;
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ti,max-div = <4>;
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reg = <0x0108>;
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ti,index-power-of-two;
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};
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abe_iclk: abe_iclk {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&aess_fclk>;
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ti,bit-shift = <24>;
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reg = <0x0528>;
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ti,dividers = <2>, <1>;
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};
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abe_lp_clk_div: abe_lp_clk_div {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_abe_m2x2_ck>;
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clock-mult = <1>;
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clock-div = <16>;
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};
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dpll_abe_m3x2_ck: dpll_abe_m3x2_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_abe_x2_ck>;
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ti,max-div = <31>;
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reg = <0x01f4>;
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ti,index-starts-at-one;
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};
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dpll_core_byp_mux: dpll_core_byp_mux {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&sys_clkin>, <&dpll_abe_m3x2_ck>;
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ti,bit-shift = <23>;
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reg = <0x012c>;
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};
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dpll_core_ck: dpll_core_ck {
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#clock-cells = <0>;
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compatible = "ti,omap4-dpll-core-clock";
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clocks = <&sys_clkin>, <&dpll_core_byp_mux>;
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reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
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};
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dpll_core_x2_ck: dpll_core_x2_ck {
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#clock-cells = <0>;
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compatible = "ti,omap4-dpll-x2-clock";
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clocks = <&dpll_core_ck>;
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};
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dpll_core_h21x2_ck: dpll_core_h21x2_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_core_x2_ck>;
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ti,max-div = <63>;
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reg = <0x0150>;
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ti,index-starts-at-one;
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};
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c2c_fclk: c2c_fclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_core_h21x2_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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c2c_iclk: c2c_iclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&c2c_fclk>;
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clock-mult = <1>;
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clock-div = <2>;
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};
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dpll_core_h11x2_ck: dpll_core_h11x2_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_core_x2_ck>;
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ti,max-div = <63>;
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reg = <0x0138>;
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ti,index-starts-at-one;
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};
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dpll_core_h12x2_ck: dpll_core_h12x2_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_core_x2_ck>;
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ti,max-div = <63>;
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reg = <0x013c>;
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ti,index-starts-at-one;
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};
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dpll_core_h13x2_ck: dpll_core_h13x2_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_core_x2_ck>;
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ti,max-div = <63>;
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reg = <0x0140>;
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ti,index-starts-at-one;
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};
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dpll_core_h14x2_ck: dpll_core_h14x2_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_core_x2_ck>;
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ti,max-div = <63>;
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reg = <0x0144>;
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ti,index-starts-at-one;
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};
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dpll_core_h22x2_ck: dpll_core_h22x2_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_core_x2_ck>;
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ti,max-div = <63>;
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reg = <0x0154>;
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ti,index-starts-at-one;
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};
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dpll_core_h23x2_ck: dpll_core_h23x2_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_core_x2_ck>;
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ti,max-div = <63>;
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reg = <0x0158>;
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ti,index-starts-at-one;
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};
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dpll_core_h24x2_ck: dpll_core_h24x2_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_core_x2_ck>;
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ti,max-div = <63>;
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reg = <0x015c>;
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ti,index-starts-at-one;
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};
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dpll_core_m2_ck: dpll_core_m2_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_core_ck>;
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ti,max-div = <31>;
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reg = <0x0130>;
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ti,index-starts-at-one;
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};
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dpll_core_m3x2_ck: dpll_core_m3x2_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_core_x2_ck>;
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ti,max-div = <31>;
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reg = <0x0134>;
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ti,index-starts-at-one;
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};
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iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_core_h12x2_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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dpll_iva_byp_mux: dpll_iva_byp_mux {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&sys_clkin>, <&iva_dpll_hs_clk_div>;
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ti,bit-shift = <23>;
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reg = <0x01ac>;
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};
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dpll_iva_ck: dpll_iva_ck {
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#clock-cells = <0>;
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compatible = "ti,omap4-dpll-clock";
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clocks = <&sys_clkin>, <&dpll_iva_byp_mux>;
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reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
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};
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dpll_iva_x2_ck: dpll_iva_x2_ck {
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#clock-cells = <0>;
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compatible = "ti,omap4-dpll-x2-clock";
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clocks = <&dpll_iva_ck>;
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};
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dpll_iva_h11x2_ck: dpll_iva_h11x2_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_iva_x2_ck>;
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ti,max-div = <63>;
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reg = <0x01b8>;
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ti,index-starts-at-one;
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};
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dpll_iva_h12x2_ck: dpll_iva_h12x2_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_iva_x2_ck>;
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ti,max-div = <63>;
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reg = <0x01bc>;
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ti,index-starts-at-one;
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};
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mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_core_h12x2_ck>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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dpll_mpu_ck: dpll_mpu_ck {
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#clock-cells = <0>;
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compatible = "ti,omap5-mpu-dpll-clock";
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clocks = <&sys_clkin>, <&mpu_dpll_hs_clk_div>;
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reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
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};
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dpll_mpu_m2_ck: dpll_mpu_m2_ck {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&dpll_mpu_ck>;
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ti,max-div = <31>;
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reg = <0x0170>;
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ti,index-starts-at-one;
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};
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per_dpll_hs_clk_div: per_dpll_hs_clk_div {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_abe_m3x2_ck>;
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clock-mult = <1>;
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clock-div = <2>;
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};
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usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&dpll_abe_m3x2_ck>;
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clock-mult = <1>;
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clock-div = <3>;
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};
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l3_iclk_div: l3_iclk_div {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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ti,max-div = <2>;
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ti,bit-shift = <4>;
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reg = <0x100>;
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clocks = <&dpll_core_h12x2_ck>;
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ti,index-power-of-two;
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};
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gpu_l3_iclk: gpu_l3_iclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clocks = <&l3_iclk_div>;
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clock-mult = <1>;
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clock-div = <1>;
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};
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l4_root_clk_div: l4_root_clk_div {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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ti,max-div = <2>;
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ti,bit-shift = <8>;
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reg = <0x100>;
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clocks = <&l3_iclk_div>;
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ti,index-power-of-two;
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};
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slimbus1_slimbus_clk: slimbus1_slimbus_clk {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&slimbus_clk>;
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ti,bit-shift = <11>;
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reg = <0x0560>;
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};
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aess_fclk: aess_fclk {
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#clock-cells = <0>;
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compatible = "ti,divider-clock";
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clocks = <&abe_clk>;
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ti,bit-shift = <24>;
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ti,max-div = <2>;
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reg = <0x0528>;
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};
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dmic_sync_mux_ck: dmic_sync_mux_ck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
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ti,bit-shift = <26>;
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reg = <0x0538>;
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};
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dmic_gfclk: dmic_gfclk {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&dmic_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
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ti,bit-shift = <24>;
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reg = <0x0538>;
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};
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mcasp_sync_mux_ck: mcasp_sync_mux_ck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
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ti,bit-shift = <26>;
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reg = <0x0540>;
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};
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mcasp_gfclk: mcasp_gfclk {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&mcasp_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
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ti,bit-shift = <24>;
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reg = <0x0540>;
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};
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mcbsp1_sync_mux_ck: mcbsp1_sync_mux_ck {
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#clock-cells = <0>;
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compatible = "ti,mux-clock";
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clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
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ti,bit-shift = <26>;
|
|
reg = <0x0548>;
|
|
};
|
|
|
|
mcbsp1_gfclk: mcbsp1_gfclk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&mcbsp1_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
|
|
ti,bit-shift = <24>;
|
|
reg = <0x0548>;
|
|
};
|
|
|
|
mcbsp2_sync_mux_ck: mcbsp2_sync_mux_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
|
|
ti,bit-shift = <26>;
|
|
reg = <0x0550>;
|
|
};
|
|
|
|
mcbsp2_gfclk: mcbsp2_gfclk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&mcbsp2_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
|
|
ti,bit-shift = <24>;
|
|
reg = <0x0550>;
|
|
};
|
|
|
|
mcbsp3_sync_mux_ck: mcbsp3_sync_mux_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&abe_24m_fclk>, <&dss_syc_gfclk_div>, <&func_24m_clk>;
|
|
ti,bit-shift = <26>;
|
|
reg = <0x0558>;
|
|
};
|
|
|
|
mcbsp3_gfclk: mcbsp3_gfclk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&mcbsp3_sync_mux_ck>, <&pad_clks_ck>, <&slimbus_clk>;
|
|
ti,bit-shift = <24>;
|
|
reg = <0x0558>;
|
|
};
|
|
|
|
timer5_gfclk_mux: timer5_gfclk_mux {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
|
|
ti,bit-shift = <24>;
|
|
reg = <0x0568>;
|
|
};
|
|
|
|
timer6_gfclk_mux: timer6_gfclk_mux {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
|
|
ti,bit-shift = <24>;
|
|
reg = <0x0570>;
|
|
};
|
|
|
|
timer7_gfclk_mux: timer7_gfclk_mux {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
|
|
ti,bit-shift = <24>;
|
|
reg = <0x0578>;
|
|
};
|
|
|
|
timer8_gfclk_mux: timer8_gfclk_mux {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&dss_syc_gfclk_div>, <&sys_32k_ck>;
|
|
ti,bit-shift = <24>;
|
|
reg = <0x0580>;
|
|
};
|
|
|
|
dummy_ck: dummy_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-clock";
|
|
clock-frequency = <0>;
|
|
};
|
|
};
|
|
&prm_clocks {
|
|
sys_clkin: sys_clkin {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&virt_12000000_ck>, <&virt_13000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
|
|
reg = <0x0110>;
|
|
ti,index-starts-at-one;
|
|
};
|
|
|
|
abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&sys_clkin>, <&sys_32k_ck>;
|
|
reg = <0x0108>;
|
|
};
|
|
|
|
abe_dpll_clk_mux: abe_dpll_clk_mux {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&sys_clkin>, <&sys_32k_ck>;
|
|
reg = <0x010c>;
|
|
};
|
|
|
|
custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&sys_clkin>;
|
|
clock-mult = <1>;
|
|
clock-div = <2>;
|
|
};
|
|
|
|
dss_syc_gfclk_div: dss_syc_gfclk_div {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&sys_clkin>;
|
|
clock-mult = <1>;
|
|
clock-div = <1>;
|
|
};
|
|
|
|
wkupaon_iclk_mux: wkupaon_iclk_mux {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&sys_clkin>, <&abe_lp_clk_div>;
|
|
reg = <0x0108>;
|
|
};
|
|
|
|
l3instr_ts_gclk_div: l3instr_ts_gclk_div {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&wkupaon_iclk_mux>;
|
|
clock-mult = <1>;
|
|
clock-div = <1>;
|
|
};
|
|
|
|
gpio1_dbclk: gpio1_dbclk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&sys_32k_ck>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x1938>;
|
|
};
|
|
|
|
timer1_gfclk_mux: timer1_gfclk_mux {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&sys_clkin>, <&sys_32k_ck>;
|
|
ti,bit-shift = <24>;
|
|
reg = <0x1940>;
|
|
};
|
|
};
|
|
&cm_core_clocks {
|
|
|
|
dpll_per_byp_mux: dpll_per_byp_mux {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&sys_clkin>, <&per_dpll_hs_clk_div>;
|
|
ti,bit-shift = <23>;
|
|
reg = <0x014c>;
|
|
};
|
|
|
|
dpll_per_ck: dpll_per_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap4-dpll-clock";
|
|
clocks = <&sys_clkin>, <&dpll_per_byp_mux>;
|
|
reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
|
|
};
|
|
|
|
dpll_per_x2_ck: dpll_per_x2_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap4-dpll-x2-clock";
|
|
clocks = <&dpll_per_ck>;
|
|
};
|
|
|
|
dpll_per_h11x2_ck: dpll_per_h11x2_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&dpll_per_x2_ck>;
|
|
ti,max-div = <63>;
|
|
reg = <0x0158>;
|
|
ti,index-starts-at-one;
|
|
};
|
|
|
|
dpll_per_h12x2_ck: dpll_per_h12x2_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&dpll_per_x2_ck>;
|
|
ti,max-div = <63>;
|
|
reg = <0x015c>;
|
|
ti,index-starts-at-one;
|
|
};
|
|
|
|
dpll_per_h14x2_ck: dpll_per_h14x2_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&dpll_per_x2_ck>;
|
|
ti,max-div = <63>;
|
|
reg = <0x0164>;
|
|
ti,index-starts-at-one;
|
|
};
|
|
|
|
dpll_per_m2_ck: dpll_per_m2_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&dpll_per_ck>;
|
|
ti,max-div = <31>;
|
|
reg = <0x0150>;
|
|
ti,index-starts-at-one;
|
|
};
|
|
|
|
dpll_per_m2x2_ck: dpll_per_m2x2_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&dpll_per_x2_ck>;
|
|
ti,max-div = <31>;
|
|
reg = <0x0150>;
|
|
ti,index-starts-at-one;
|
|
};
|
|
|
|
dpll_per_m3x2_ck: dpll_per_m3x2_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&dpll_per_x2_ck>;
|
|
ti,max-div = <31>;
|
|
reg = <0x0154>;
|
|
ti,index-starts-at-one;
|
|
};
|
|
|
|
dpll_unipro1_ck: dpll_unipro1_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap4-dpll-clock";
|
|
clocks = <&sys_clkin>, <&sys_clkin>;
|
|
reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
|
|
};
|
|
|
|
dpll_unipro1_clkdcoldo: dpll_unipro1_clkdcoldo {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&dpll_unipro1_ck>;
|
|
clock-mult = <1>;
|
|
clock-div = <1>;
|
|
};
|
|
|
|
dpll_unipro1_m2_ck: dpll_unipro1_m2_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&dpll_unipro1_ck>;
|
|
ti,max-div = <127>;
|
|
reg = <0x0210>;
|
|
ti,index-starts-at-one;
|
|
};
|
|
|
|
dpll_unipro2_ck: dpll_unipro2_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap4-dpll-clock";
|
|
clocks = <&sys_clkin>, <&sys_clkin>;
|
|
reg = <0x01c0>, <0x01c4>, <0x01cc>, <0x01c8>;
|
|
};
|
|
|
|
dpll_unipro2_clkdcoldo: dpll_unipro2_clkdcoldo {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&dpll_unipro2_ck>;
|
|
clock-mult = <1>;
|
|
clock-div = <1>;
|
|
};
|
|
|
|
dpll_unipro2_m2_ck: dpll_unipro2_m2_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&dpll_unipro2_ck>;
|
|
ti,max-div = <127>;
|
|
reg = <0x01d0>;
|
|
ti,index-starts-at-one;
|
|
};
|
|
|
|
dpll_usb_byp_mux: dpll_usb_byp_mux {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&sys_clkin>, <&usb_dpll_hs_clk_div>;
|
|
ti,bit-shift = <23>;
|
|
reg = <0x018c>;
|
|
};
|
|
|
|
dpll_usb_ck: dpll_usb_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,omap4-dpll-j-type-clock";
|
|
clocks = <&sys_clkin>, <&dpll_usb_byp_mux>;
|
|
reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
|
|
};
|
|
|
|
dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&dpll_usb_ck>;
|
|
clock-mult = <1>;
|
|
clock-div = <1>;
|
|
};
|
|
|
|
dpll_usb_m2_ck: dpll_usb_m2_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&dpll_usb_ck>;
|
|
ti,max-div = <127>;
|
|
reg = <0x0190>;
|
|
ti,index-starts-at-one;
|
|
};
|
|
|
|
func_128m_clk: func_128m_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&dpll_per_h11x2_ck>;
|
|
clock-mult = <1>;
|
|
clock-div = <2>;
|
|
};
|
|
|
|
func_12m_fclk: func_12m_fclk {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&dpll_per_m2x2_ck>;
|
|
clock-mult = <1>;
|
|
clock-div = <16>;
|
|
};
|
|
|
|
func_24m_clk: func_24m_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&dpll_per_m2_ck>;
|
|
clock-mult = <1>;
|
|
clock-div = <4>;
|
|
};
|
|
|
|
func_48m_fclk: func_48m_fclk {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&dpll_per_m2x2_ck>;
|
|
clock-mult = <1>;
|
|
clock-div = <4>;
|
|
};
|
|
|
|
func_96m_fclk: func_96m_fclk {
|
|
#clock-cells = <0>;
|
|
compatible = "fixed-factor-clock";
|
|
clocks = <&dpll_per_m2x2_ck>;
|
|
clock-mult = <1>;
|
|
clock-div = <2>;
|
|
};
|
|
|
|
l3init_60m_fclk: l3init_60m_fclk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&dpll_usb_m2_ck>;
|
|
reg = <0x0104>;
|
|
ti,dividers = <1>, <8>;
|
|
};
|
|
|
|
dss_32khz_clk: dss_32khz_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&sys_32k_ck>;
|
|
ti,bit-shift = <11>;
|
|
reg = <0x1420>;
|
|
};
|
|
|
|
dss_48mhz_clk: dss_48mhz_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&func_48m_fclk>;
|
|
ti,bit-shift = <9>;
|
|
reg = <0x1420>;
|
|
};
|
|
|
|
dss_dss_clk: dss_dss_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&dpll_per_h12x2_ck>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x1420>;
|
|
ti,set-rate-parent;
|
|
};
|
|
|
|
dss_sys_clk: dss_sys_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&dss_syc_gfclk_div>;
|
|
ti,bit-shift = <10>;
|
|
reg = <0x1420>;
|
|
};
|
|
|
|
gpio2_dbclk: gpio2_dbclk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&sys_32k_ck>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x1060>;
|
|
};
|
|
|
|
gpio3_dbclk: gpio3_dbclk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&sys_32k_ck>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x1068>;
|
|
};
|
|
|
|
gpio4_dbclk: gpio4_dbclk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&sys_32k_ck>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x1070>;
|
|
};
|
|
|
|
gpio5_dbclk: gpio5_dbclk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&sys_32k_ck>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x1078>;
|
|
};
|
|
|
|
gpio6_dbclk: gpio6_dbclk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&sys_32k_ck>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x1080>;
|
|
};
|
|
|
|
gpio7_dbclk: gpio7_dbclk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&sys_32k_ck>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x1110>;
|
|
};
|
|
|
|
gpio8_dbclk: gpio8_dbclk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&sys_32k_ck>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x1118>;
|
|
};
|
|
|
|
iss_ctrlclk: iss_ctrlclk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&func_96m_fclk>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x1320>;
|
|
};
|
|
|
|
lli_txphy_clk: lli_txphy_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&dpll_unipro1_clkdcoldo>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x0f20>;
|
|
};
|
|
|
|
lli_txphy_ls_clk: lli_txphy_ls_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&dpll_unipro1_m2_ck>;
|
|
ti,bit-shift = <9>;
|
|
reg = <0x0f20>;
|
|
};
|
|
|
|
mmc1_32khz_clk: mmc1_32khz_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&sys_32k_ck>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x1628>;
|
|
};
|
|
|
|
sata_ref_clk: sata_ref_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&sys_clkin>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x1688>;
|
|
};
|
|
|
|
usb_host_hs_hsic480m_p1_clk: usb_host_hs_hsic480m_p1_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&dpll_usb_m2_ck>;
|
|
ti,bit-shift = <13>;
|
|
reg = <0x1658>;
|
|
};
|
|
|
|
usb_host_hs_hsic480m_p2_clk: usb_host_hs_hsic480m_p2_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&dpll_usb_m2_ck>;
|
|
ti,bit-shift = <14>;
|
|
reg = <0x1658>;
|
|
};
|
|
|
|
usb_host_hs_hsic480m_p3_clk: usb_host_hs_hsic480m_p3_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&dpll_usb_m2_ck>;
|
|
ti,bit-shift = <7>;
|
|
reg = <0x1658>;
|
|
};
|
|
|
|
usb_host_hs_hsic60m_p1_clk: usb_host_hs_hsic60m_p1_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&l3init_60m_fclk>;
|
|
ti,bit-shift = <11>;
|
|
reg = <0x1658>;
|
|
};
|
|
|
|
usb_host_hs_hsic60m_p2_clk: usb_host_hs_hsic60m_p2_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&l3init_60m_fclk>;
|
|
ti,bit-shift = <12>;
|
|
reg = <0x1658>;
|
|
};
|
|
|
|
usb_host_hs_hsic60m_p3_clk: usb_host_hs_hsic60m_p3_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&l3init_60m_fclk>;
|
|
ti,bit-shift = <6>;
|
|
reg = <0x1658>;
|
|
};
|
|
|
|
utmi_p1_gfclk: utmi_p1_gfclk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&l3init_60m_fclk>, <&xclk60mhsp1_ck>;
|
|
ti,bit-shift = <24>;
|
|
reg = <0x1658>;
|
|
};
|
|
|
|
usb_host_hs_utmi_p1_clk: usb_host_hs_utmi_p1_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&utmi_p1_gfclk>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x1658>;
|
|
};
|
|
|
|
utmi_p2_gfclk: utmi_p2_gfclk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&l3init_60m_fclk>, <&xclk60mhsp2_ck>;
|
|
ti,bit-shift = <25>;
|
|
reg = <0x1658>;
|
|
};
|
|
|
|
usb_host_hs_utmi_p2_clk: usb_host_hs_utmi_p2_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&utmi_p2_gfclk>;
|
|
ti,bit-shift = <9>;
|
|
reg = <0x1658>;
|
|
};
|
|
|
|
usb_host_hs_utmi_p3_clk: usb_host_hs_utmi_p3_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&l3init_60m_fclk>;
|
|
ti,bit-shift = <10>;
|
|
reg = <0x1658>;
|
|
};
|
|
|
|
usb_otg_ss_refclk960m: usb_otg_ss_refclk960m {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&dpll_usb_clkdcoldo>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x16f0>;
|
|
};
|
|
|
|
usb_phy_cm_clk32k: usb_phy_cm_clk32k {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&sys_32k_ck>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x0640>;
|
|
};
|
|
|
|
usb_tll_hs_usb_ch0_clk: usb_tll_hs_usb_ch0_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&l3init_60m_fclk>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x1668>;
|
|
};
|
|
|
|
usb_tll_hs_usb_ch1_clk: usb_tll_hs_usb_ch1_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&l3init_60m_fclk>;
|
|
ti,bit-shift = <9>;
|
|
reg = <0x1668>;
|
|
};
|
|
|
|
usb_tll_hs_usb_ch2_clk: usb_tll_hs_usb_ch2_clk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,gate-clock";
|
|
clocks = <&l3init_60m_fclk>;
|
|
ti,bit-shift = <10>;
|
|
reg = <0x1668>;
|
|
};
|
|
|
|
fdif_fclk: fdif_fclk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&dpll_per_h11x2_ck>;
|
|
ti,bit-shift = <24>;
|
|
ti,max-div = <2>;
|
|
reg = <0x1328>;
|
|
};
|
|
|
|
gpu_core_gclk_mux: gpu_core_gclk_mux {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
|
|
ti,bit-shift = <24>;
|
|
reg = <0x1520>;
|
|
};
|
|
|
|
gpu_hyd_gclk_mux: gpu_hyd_gclk_mux {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>;
|
|
ti,bit-shift = <25>;
|
|
reg = <0x1520>;
|
|
};
|
|
|
|
hsi_fclk: hsi_fclk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&dpll_per_m2x2_ck>;
|
|
ti,bit-shift = <24>;
|
|
ti,max-div = <2>;
|
|
reg = <0x1638>;
|
|
};
|
|
|
|
mmc1_fclk_mux: mmc1_fclk_mux {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
|
|
ti,bit-shift = <24>;
|
|
reg = <0x1628>;
|
|
};
|
|
|
|
mmc1_fclk: mmc1_fclk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&mmc1_fclk_mux>;
|
|
ti,bit-shift = <25>;
|
|
ti,max-div = <2>;
|
|
reg = <0x1628>;
|
|
};
|
|
|
|
mmc2_fclk_mux: mmc2_fclk_mux {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&func_128m_clk>, <&dpll_per_m2x2_ck>;
|
|
ti,bit-shift = <24>;
|
|
reg = <0x1630>;
|
|
};
|
|
|
|
mmc2_fclk: mmc2_fclk {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&mmc2_fclk_mux>;
|
|
ti,bit-shift = <25>;
|
|
ti,max-div = <2>;
|
|
reg = <0x1630>;
|
|
};
|
|
|
|
timer10_gfclk_mux: timer10_gfclk_mux {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&sys_clkin>, <&sys_32k_ck>;
|
|
ti,bit-shift = <24>;
|
|
reg = <0x1028>;
|
|
};
|
|
|
|
timer11_gfclk_mux: timer11_gfclk_mux {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&sys_clkin>, <&sys_32k_ck>;
|
|
ti,bit-shift = <24>;
|
|
reg = <0x1030>;
|
|
};
|
|
|
|
timer2_gfclk_mux: timer2_gfclk_mux {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&sys_clkin>, <&sys_32k_ck>;
|
|
ti,bit-shift = <24>;
|
|
reg = <0x1038>;
|
|
};
|
|
|
|
timer3_gfclk_mux: timer3_gfclk_mux {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&sys_clkin>, <&sys_32k_ck>;
|
|
ti,bit-shift = <24>;
|
|
reg = <0x1040>;
|
|
};
|
|
|
|
timer4_gfclk_mux: timer4_gfclk_mux {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&sys_clkin>, <&sys_32k_ck>;
|
|
ti,bit-shift = <24>;
|
|
reg = <0x1048>;
|
|
};
|
|
|
|
timer9_gfclk_mux: timer9_gfclk_mux {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&sys_clkin>, <&sys_32k_ck>;
|
|
ti,bit-shift = <24>;
|
|
reg = <0x1050>;
|
|
};
|
|
};
|
|
|
|
&cm_core_clockdomains {
|
|
l3init_clkdm: l3init_clkdm {
|
|
compatible = "ti,clockdomain";
|
|
clocks = <&dpll_usb_ck>;
|
|
};
|
|
};
|
|
|
|
&scrm_clocks {
|
|
auxclk0_src_gate_ck: auxclk0_src_gate_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-no-wait-gate-clock";
|
|
clocks = <&dpll_core_m3x2_ck>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x0310>;
|
|
};
|
|
|
|
auxclk0_src_mux_ck: auxclk0_src_mux_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-mux-clock";
|
|
clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
|
|
ti,bit-shift = <1>;
|
|
reg = <0x0310>;
|
|
};
|
|
|
|
auxclk0_src_ck: auxclk0_src_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-clock";
|
|
clocks = <&auxclk0_src_gate_ck>, <&auxclk0_src_mux_ck>;
|
|
};
|
|
|
|
auxclk0_ck: auxclk0_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&auxclk0_src_ck>;
|
|
ti,bit-shift = <16>;
|
|
ti,max-div = <16>;
|
|
reg = <0x0310>;
|
|
};
|
|
|
|
auxclk1_src_gate_ck: auxclk1_src_gate_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-no-wait-gate-clock";
|
|
clocks = <&dpll_core_m3x2_ck>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x0314>;
|
|
};
|
|
|
|
auxclk1_src_mux_ck: auxclk1_src_mux_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-mux-clock";
|
|
clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
|
|
ti,bit-shift = <1>;
|
|
reg = <0x0314>;
|
|
};
|
|
|
|
auxclk1_src_ck: auxclk1_src_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-clock";
|
|
clocks = <&auxclk1_src_gate_ck>, <&auxclk1_src_mux_ck>;
|
|
};
|
|
|
|
auxclk1_ck: auxclk1_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&auxclk1_src_ck>;
|
|
ti,bit-shift = <16>;
|
|
ti,max-div = <16>;
|
|
reg = <0x0314>;
|
|
};
|
|
|
|
auxclk2_src_gate_ck: auxclk2_src_gate_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-no-wait-gate-clock";
|
|
clocks = <&dpll_core_m3x2_ck>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x0318>;
|
|
};
|
|
|
|
auxclk2_src_mux_ck: auxclk2_src_mux_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-mux-clock";
|
|
clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
|
|
ti,bit-shift = <1>;
|
|
reg = <0x0318>;
|
|
};
|
|
|
|
auxclk2_src_ck: auxclk2_src_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-clock";
|
|
clocks = <&auxclk2_src_gate_ck>, <&auxclk2_src_mux_ck>;
|
|
};
|
|
|
|
auxclk2_ck: auxclk2_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&auxclk2_src_ck>;
|
|
ti,bit-shift = <16>;
|
|
ti,max-div = <16>;
|
|
reg = <0x0318>;
|
|
};
|
|
|
|
auxclk3_src_gate_ck: auxclk3_src_gate_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-no-wait-gate-clock";
|
|
clocks = <&dpll_core_m3x2_ck>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x031c>;
|
|
};
|
|
|
|
auxclk3_src_mux_ck: auxclk3_src_mux_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-mux-clock";
|
|
clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
|
|
ti,bit-shift = <1>;
|
|
reg = <0x031c>;
|
|
};
|
|
|
|
auxclk3_src_ck: auxclk3_src_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-clock";
|
|
clocks = <&auxclk3_src_gate_ck>, <&auxclk3_src_mux_ck>;
|
|
};
|
|
|
|
auxclk3_ck: auxclk3_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&auxclk3_src_ck>;
|
|
ti,bit-shift = <16>;
|
|
ti,max-div = <16>;
|
|
reg = <0x031c>;
|
|
};
|
|
|
|
auxclk4_src_gate_ck: auxclk4_src_gate_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-no-wait-gate-clock";
|
|
clocks = <&dpll_core_m3x2_ck>;
|
|
ti,bit-shift = <8>;
|
|
reg = <0x0320>;
|
|
};
|
|
|
|
auxclk4_src_mux_ck: auxclk4_src_mux_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-mux-clock";
|
|
clocks = <&sys_clkin>, <&dpll_core_m3x2_ck>, <&dpll_per_m3x2_ck>;
|
|
ti,bit-shift = <1>;
|
|
reg = <0x0320>;
|
|
};
|
|
|
|
auxclk4_src_ck: auxclk4_src_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,composite-clock";
|
|
clocks = <&auxclk4_src_gate_ck>, <&auxclk4_src_mux_ck>;
|
|
};
|
|
|
|
auxclk4_ck: auxclk4_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,divider-clock";
|
|
clocks = <&auxclk4_src_ck>;
|
|
ti,bit-shift = <16>;
|
|
ti,max-div = <16>;
|
|
reg = <0x0320>;
|
|
};
|
|
|
|
auxclkreq0_ck: auxclkreq0_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
|
|
ti,bit-shift = <2>;
|
|
reg = <0x0210>;
|
|
};
|
|
|
|
auxclkreq1_ck: auxclkreq1_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
|
|
ti,bit-shift = <2>;
|
|
reg = <0x0214>;
|
|
};
|
|
|
|
auxclkreq2_ck: auxclkreq2_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
|
|
ti,bit-shift = <2>;
|
|
reg = <0x0218>;
|
|
};
|
|
|
|
auxclkreq3_ck: auxclkreq3_ck {
|
|
#clock-cells = <0>;
|
|
compatible = "ti,mux-clock";
|
|
clocks = <&auxclk0_ck>, <&auxclk1_ck>, <&auxclk2_ck>, <&auxclk3_ck>, <&auxclk4_ck>;
|
|
ti,bit-shift = <2>;
|
|
reg = <0x021c>;
|
|
};
|
|
};
|