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b2af8e58a0
Relaxed the license on the dtsi to permit use in other projects. Signed-off-by: Lars Persson <larper@axis.com> Signed-off-by: Olof Johansson <olof@lixom.net>
271 lines
7.0 KiB
Plaintext
271 lines
7.0 KiB
Plaintext
/*
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* Device Tree Source for the Axis ARTPEC-6 SoC
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "skeleton.dtsi"
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/ {
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compatible = "axis,artpec6";
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interrupt-parent = <&intc>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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next-level-cache = <&pl310>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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next-level-cache = <&pl310>;
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};
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};
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syscon {
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compatible = "axis,artpec6-syscon", "syscon";
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reg = <0xf8000000 0x48>;
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};
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psci {
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compatible = "arm,psci-0.2", "arm,psci";
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method = "smc";
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psci_version = <0x84000000>;
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cpu_on = <0x84000003>;
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system_reset = <0x84000009>;
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};
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scu@faf00000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0xfaf00000 0x58>;
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};
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/* Main external clock driving CPU and peripherals */
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ext_clk: ext_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <50000000>;
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};
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/* PLL1 is used by CPU and some peripherals */
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pll1_clk: pll1_clk@f8000000 {
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#clock-cells = <0>;
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compatible = "axis,artpec6-pll1-clock";
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reg = <0xf8000000 4>;
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clocks = <&ext_clk>;
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};
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cpu_clk: cpu_clk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <1>;
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clocks = <&pll1_clk>;
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clock-output-names = "cpu_clk";
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};
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cpu_clkdiv2: cpu_clkdiv2 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <2>;
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clock-mult = <1>;
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clocks = <&cpu_clk>;
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};
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cpu_clkdiv4: cpu_clkdiv4 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <4>;
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clock-mult = <1>;
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clocks = <&cpu_clk>;
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};
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apb_pclk: apb_pclk {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <8>;
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clock-mult = <1>;
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clocks = <&cpu_clk>;
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clock-output-names = "apb_pclk";
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};
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/* PLL2 is used by a number of peripherals, including UDL */
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pll2: pll2 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <1>;
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clock-mult = <24>;
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clocks = <&ext_clk>;
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};
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/* PLL2DIV2 is used by the Fractional Clock Divider, for i2s */
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pll2div2: pll2div2 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <2>;
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clock-mult = <1>;
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clocks = <&pll2>;
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};
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pll2div12: pll2div12 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <12>;
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clock-mult = <1>;
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clocks = <&pll2>;
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};
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pll2div24: pll2div24 {
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#clock-cells = <0>;
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compatible = "fixed-factor-clock";
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clock-div = <24>;
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clock-mult = <1>;
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clocks = <&pll2>;
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clock-output-names = "uart_clk";
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};
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gtimer@faf00200 {
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compatible = "arm,cortex-a9-global-timer";
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reg = <0xfaf00200 0x20>;
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interrupts = <GIC_PPI 11 0xf01>;
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clocks = <&cpu_clkdiv2>;
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};
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timer@faf00600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0xfaf00600 0x20>;
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interrupts = <GIC_PPI 13 0xf04>;
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clocks = <&cpu_clkdiv2>;
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status = "disabled";
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};
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intc: interrupt-controller@faf01000 {
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interrupt-controller;
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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reg = < 0xfaf01000 0x1000 >, < 0xfaf00100 0x0100 >;
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};
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pl310: cache-controller@faf10000 {
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compatible = "arm,pl310-cache";
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cache-unified;
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cache-level = <2>;
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reg = <0xfaf10000 0x1000>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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arm,data-latency = <1 1 1>;
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arm,tag-latency = <1 1 1>;
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arm,filter-ranges = <0x0 0x80000000>;
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};
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&intc>;
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};
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amba@0 {
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compatible = "simple-bus";
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#address-cells = <0x1>;
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#size-cells = <0x1>;
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interrupt-parent = <&intc>;
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ranges;
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dma-ranges = <0x80000000 0x00000000 0x40000000>;
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dma-coherent;
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ethernet: ethernet@f8010000 {
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clock-names = "phy_ref_clk", "apb_pclk";
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clocks = <&ext_clk>, <&apb_pclk>;
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compatible = "snps,dwc-qos-ethernet-4.10";
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interrupt-parent = <&intc>;
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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reg = <0xf8010000 0x4000>;
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snps,write-requests = <2>;
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snps,read-requests = <16>;
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snps,txpbl = <8>;
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snps,rxpbl = <2>;
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status = "disabled";
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};
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uart0: serial@f8036000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xf8036000 0x1000>;
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interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pll2div24>, <&apb_pclk>;
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clock-names = "uart_clk", "apb_pclk";
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status = "disabled";
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};
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uart1: serial@f8037000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xf8037000 0x1000>;
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interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pll2div24>, <&apb_pclk>;
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clock-names = "uart_clk", "apb_pclk";
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status = "disabled";
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};
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uart2: serial@f8038000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xf8038000 0x1000>;
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interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pll2div24>, <&apb_pclk>;
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clock-names = "uart_clk", "apb_pclk";
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status = "disabled";
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};
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uart3: serial@f8039000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0xf8039000 0x1000>;
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interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&pll2div24>, <&apb_pclk>;
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clock-names = "uart_clk", "apb_pclk";
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status = "disabled";
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};
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};
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};
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