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04a341138d
We would allocate one specific exception stack for each kind of non-base exceptions for every CPU. For ppc32 the CPU hard ID is used as the subscript to get the specific exception stack for one CPU. But for an UP kernel, there is only one element in the each kind of exception stack array. We would get stuck if the CPU hard ID is not equal to '0'. So in this case we should use the subscript '0' no matter what the CPU hard ID is. Signed-off-by: Kevin Hao <haokexin@gmail.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
683 lines
17 KiB
C
683 lines
17 KiB
C
/*
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* Derived from arch/i386/kernel/irq.c
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* Copyright (C) 1992 Linus Torvalds
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* Adapted from arch/i386 by Gary Thomas
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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* Updated and modified by Cort Dougan <cort@fsmlabs.com>
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* Copyright (C) 1996-2001 Cort Dougan
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* Adapted for Power Macintosh by Paul Mackerras
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* Copyright (C) 1996 Paul Mackerras (paulus@cs.anu.edu.au)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* This file contains the code used by various IRQ handling routines:
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* asking for different IRQ's should be done through these routines
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* instead of just grabbing them. Thus setups with different IRQ numbers
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* shouldn't result in any weird surprises, and installing new handlers
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* should be easier.
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*
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* The MPC8xx has an interrupt mask in the SIU. If a bit is set, the
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* interrupt is _enabled_. As expected, IRQ0 is bit 0 in the 32-bit
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* mask register (of which only 16 are defined), hence the weird shifting
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* and complement of the cached_irq_mask. I want to be able to stuff
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* this right into the SIU SMASK register.
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* Many of the prep/chrp functions are conditional compiled on CONFIG_8xx
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* to reduce code space and undefined function references.
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*/
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#undef DEBUG
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#include <linux/export.h>
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#include <linux/threads.h>
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#include <linux/kernel_stat.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/ptrace.h>
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#include <linux/ioport.h>
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#include <linux/interrupt.h>
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#include <linux/timex.h>
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#include <linux/init.h>
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#include <linux/slab.h>
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#include <linux/delay.h>
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#include <linux/irq.h>
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#include <linux/seq_file.h>
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#include <linux/cpumask.h>
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#include <linux/profile.h>
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#include <linux/bitops.h>
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#include <linux/list.h>
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#include <linux/radix-tree.h>
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#include <linux/mutex.h>
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#include <linux/bootmem.h>
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#include <linux/pci.h>
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#include <linux/debugfs.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <asm/uaccess.h>
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#include <asm/io.h>
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#include <asm/pgtable.h>
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#include <asm/irq.h>
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#include <asm/cache.h>
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#include <asm/prom.h>
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#include <asm/ptrace.h>
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#include <asm/machdep.h>
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#include <asm/udbg.h>
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#include <asm/smp.h>
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#include <asm/debug.h>
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#ifdef CONFIG_PPC64
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#include <asm/paca.h>
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#include <asm/firmware.h>
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#include <asm/lv1call.h>
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#endif
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#define CREATE_TRACE_POINTS
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#include <asm/trace.h>
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DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
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EXPORT_PER_CPU_SYMBOL(irq_stat);
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int __irq_offset_value;
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#ifdef CONFIG_PPC32
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EXPORT_SYMBOL(__irq_offset_value);
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atomic_t ppc_n_lost_interrupts;
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#ifdef CONFIG_TAU_INT
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extern int tau_initialized;
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extern int tau_interrupts(int);
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#endif
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#endif /* CONFIG_PPC32 */
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#ifdef CONFIG_PPC64
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int distribute_irqs = 1;
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static inline notrace unsigned long get_irq_happened(void)
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{
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unsigned long happened;
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__asm__ __volatile__("lbz %0,%1(13)"
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: "=r" (happened) : "i" (offsetof(struct paca_struct, irq_happened)));
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return happened;
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}
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static inline notrace void set_soft_enabled(unsigned long enable)
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{
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__asm__ __volatile__("stb %0,%1(13)"
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: : "r" (enable), "i" (offsetof(struct paca_struct, soft_enabled)));
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}
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static inline notrace int decrementer_check_overflow(void)
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{
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u64 now = get_tb_or_rtc();
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u64 *next_tb = &__get_cpu_var(decrementers_next_tb);
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return now >= *next_tb;
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}
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/* This is called whenever we are re-enabling interrupts
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* and returns either 0 (nothing to do) or 500/900/280/a00/e80 if
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* there's an EE, DEC or DBELL to generate.
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*
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* This is called in two contexts: From arch_local_irq_restore()
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* before soft-enabling interrupts, and from the exception exit
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* path when returning from an interrupt from a soft-disabled to
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* a soft enabled context. In both case we have interrupts hard
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* disabled.
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*
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* We take care of only clearing the bits we handled in the
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* PACA irq_happened field since we can only re-emit one at a
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* time and we don't want to "lose" one.
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*/
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notrace unsigned int __check_irq_replay(void)
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{
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/*
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* We use local_paca rather than get_paca() to avoid all
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* the debug_smp_processor_id() business in this low level
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* function
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*/
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unsigned char happened = local_paca->irq_happened;
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/* Clear bit 0 which we wouldn't clear otherwise */
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local_paca->irq_happened &= ~PACA_IRQ_HARD_DIS;
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/*
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* Force the delivery of pending soft-disabled interrupts on PS3.
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* Any HV call will have this side effect.
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*/
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if (firmware_has_feature(FW_FEATURE_PS3_LV1)) {
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u64 tmp, tmp2;
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lv1_get_version_info(&tmp, &tmp2);
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}
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/*
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* We may have missed a decrementer interrupt. We check the
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* decrementer itself rather than the paca irq_happened field
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* in case we also had a rollover while hard disabled
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*/
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local_paca->irq_happened &= ~PACA_IRQ_DEC;
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if ((happened & PACA_IRQ_DEC) || decrementer_check_overflow())
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return 0x900;
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/* Finally check if an external interrupt happened */
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local_paca->irq_happened &= ~PACA_IRQ_EE;
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if (happened & PACA_IRQ_EE)
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return 0x500;
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#ifdef CONFIG_PPC_BOOK3E
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/* Finally check if an EPR external interrupt happened
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* this bit is typically set if we need to handle another
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* "edge" interrupt from within the MPIC "EPR" handler
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*/
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local_paca->irq_happened &= ~PACA_IRQ_EE_EDGE;
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if (happened & PACA_IRQ_EE_EDGE)
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return 0x500;
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local_paca->irq_happened &= ~PACA_IRQ_DBELL;
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if (happened & PACA_IRQ_DBELL)
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return 0x280;
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#else
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local_paca->irq_happened &= ~PACA_IRQ_DBELL;
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if (happened & PACA_IRQ_DBELL) {
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if (cpu_has_feature(CPU_FTR_HVMODE))
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return 0xe80;
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return 0xa00;
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}
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#endif /* CONFIG_PPC_BOOK3E */
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/* There should be nothing left ! */
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BUG_ON(local_paca->irq_happened != 0);
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return 0;
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}
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notrace void arch_local_irq_restore(unsigned long en)
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{
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unsigned char irq_happened;
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unsigned int replay;
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/* Write the new soft-enabled value */
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set_soft_enabled(en);
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if (!en)
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return;
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/*
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* From this point onward, we can take interrupts, preempt,
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* etc... unless we got hard-disabled. We check if an event
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* happened. If none happened, we know we can just return.
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*
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* We may have preempted before the check below, in which case
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* we are checking the "new" CPU instead of the old one. This
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* is only a problem if an event happened on the "old" CPU.
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*
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* External interrupt events will have caused interrupts to
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* be hard-disabled, so there is no problem, we
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* cannot have preempted.
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*/
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irq_happened = get_irq_happened();
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if (!irq_happened)
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return;
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/*
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* We need to hard disable to get a trusted value from
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* __check_irq_replay(). We also need to soft-disable
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* again to avoid warnings in there due to the use of
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* per-cpu variables.
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*
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* We know that if the value in irq_happened is exactly 0x01
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* then we are already hard disabled (there are other less
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* common cases that we'll ignore for now), so we skip the
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* (expensive) mtmsrd.
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*/
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if (unlikely(irq_happened != PACA_IRQ_HARD_DIS))
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__hard_irq_disable();
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#ifdef CONFIG_TRACE_IRQFLAGS
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else {
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/*
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* We should already be hard disabled here. We had bugs
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* where that wasn't the case so let's dbl check it and
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* warn if we are wrong. Only do that when IRQ tracing
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* is enabled as mfmsr() can be costly.
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*/
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if (WARN_ON(mfmsr() & MSR_EE))
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__hard_irq_disable();
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}
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#endif /* CONFIG_TRACE_IRQFLAG */
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set_soft_enabled(0);
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/*
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* Check if anything needs to be re-emitted. We haven't
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* soft-enabled yet to avoid warnings in decrementer_check_overflow
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* accessing per-cpu variables
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*/
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replay = __check_irq_replay();
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/* We can soft-enable now */
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set_soft_enabled(1);
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/*
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* And replay if we have to. This will return with interrupts
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* hard-enabled.
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*/
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if (replay) {
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__replay_interrupt(replay);
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return;
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}
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/* Finally, let's ensure we are hard enabled */
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__hard_irq_enable();
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}
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EXPORT_SYMBOL(arch_local_irq_restore);
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/*
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* This is specifically called by assembly code to re-enable interrupts
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* if they are currently disabled. This is typically called before
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* schedule() or do_signal() when returning to userspace. We do it
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* in C to avoid the burden of dealing with lockdep etc...
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*
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* NOTE: This is called with interrupts hard disabled but not marked
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* as such in paca->irq_happened, so we need to resync this.
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*/
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void notrace restore_interrupts(void)
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{
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if (irqs_disabled()) {
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local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
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local_irq_enable();
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} else
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__hard_irq_enable();
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}
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/*
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* This is a helper to use when about to go into idle low-power
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* when the latter has the side effect of re-enabling interrupts
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* (such as calling H_CEDE under pHyp).
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*
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* You call this function with interrupts soft-disabled (this is
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* already the case when ppc_md.power_save is called). The function
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* will return whether to enter power save or just return.
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*
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* In the former case, it will have notified lockdep of interrupts
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* being re-enabled and generally sanitized the lazy irq state,
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* and in the latter case it will leave with interrupts hard
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* disabled and marked as such, so the local_irq_enable() call
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* in cpu_idle() will properly re-enable everything.
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*/
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bool prep_irq_for_idle(void)
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{
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/*
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* First we need to hard disable to ensure no interrupt
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* occurs before we effectively enter the low power state
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*/
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hard_irq_disable();
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/*
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* If anything happened while we were soft-disabled,
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* we return now and do not enter the low power state.
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*/
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if (lazy_irq_pending())
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return false;
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/* Tell lockdep we are about to re-enable */
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trace_hardirqs_on();
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/*
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* Mark interrupts as soft-enabled and clear the
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* PACA_IRQ_HARD_DIS from the pending mask since we
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* are about to hard enable as well as a side effect
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* of entering the low power state.
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*/
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local_paca->irq_happened &= ~PACA_IRQ_HARD_DIS;
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local_paca->soft_enabled = 1;
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/* Tell the caller to enter the low power state */
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return true;
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}
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#endif /* CONFIG_PPC64 */
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int arch_show_interrupts(struct seq_file *p, int prec)
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{
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int j;
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#if defined(CONFIG_PPC32) && defined(CONFIG_TAU_INT)
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if (tau_initialized) {
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seq_printf(p, "%*s: ", prec, "TAU");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", tau_interrupts(j));
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seq_puts(p, " PowerPC Thermal Assist (cpu temp)\n");
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}
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#endif /* CONFIG_PPC32 && CONFIG_TAU_INT */
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seq_printf(p, "%*s: ", prec, "LOC");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", per_cpu(irq_stat, j).timer_irqs_event);
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seq_printf(p, " Local timer interrupts for timer event device\n");
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seq_printf(p, "%*s: ", prec, "LOC");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", per_cpu(irq_stat, j).timer_irqs_others);
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seq_printf(p, " Local timer interrupts for others\n");
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seq_printf(p, "%*s: ", prec, "SPU");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", per_cpu(irq_stat, j).spurious_irqs);
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seq_printf(p, " Spurious interrupts\n");
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seq_printf(p, "%*s: ", prec, "PMI");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", per_cpu(irq_stat, j).pmu_irqs);
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seq_printf(p, " Performance monitoring interrupts\n");
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seq_printf(p, "%*s: ", prec, "MCE");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", per_cpu(irq_stat, j).mce_exceptions);
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seq_printf(p, " Machine check exceptions\n");
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#ifdef CONFIG_PPC_DOORBELL
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if (cpu_has_feature(CPU_FTR_DBELL)) {
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seq_printf(p, "%*s: ", prec, "DBL");
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for_each_online_cpu(j)
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seq_printf(p, "%10u ", per_cpu(irq_stat, j).doorbell_irqs);
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seq_printf(p, " Doorbell interrupts\n");
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}
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#endif
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return 0;
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}
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/*
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* /proc/stat helpers
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*/
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u64 arch_irq_stat_cpu(unsigned int cpu)
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{
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u64 sum = per_cpu(irq_stat, cpu).timer_irqs_event;
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sum += per_cpu(irq_stat, cpu).pmu_irqs;
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sum += per_cpu(irq_stat, cpu).mce_exceptions;
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sum += per_cpu(irq_stat, cpu).spurious_irqs;
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sum += per_cpu(irq_stat, cpu).timer_irqs_others;
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#ifdef CONFIG_PPC_DOORBELL
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sum += per_cpu(irq_stat, cpu).doorbell_irqs;
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#endif
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return sum;
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}
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#ifdef CONFIG_HOTPLUG_CPU
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void migrate_irqs(void)
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{
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struct irq_desc *desc;
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unsigned int irq;
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static int warned;
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cpumask_var_t mask;
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const struct cpumask *map = cpu_online_mask;
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alloc_cpumask_var(&mask, GFP_KERNEL);
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for_each_irq_desc(irq, desc) {
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struct irq_data *data;
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struct irq_chip *chip;
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data = irq_desc_get_irq_data(desc);
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if (irqd_is_per_cpu(data))
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continue;
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chip = irq_data_get_irq_chip(data);
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cpumask_and(mask, data->affinity, map);
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if (cpumask_any(mask) >= nr_cpu_ids) {
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printk("Breaking affinity for irq %i\n", irq);
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cpumask_copy(mask, map);
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}
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if (chip->irq_set_affinity)
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chip->irq_set_affinity(data, mask, true);
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else if (desc->action && !(warned++))
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printk("Cannot set affinity for irq %i\n", irq);
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}
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free_cpumask_var(mask);
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local_irq_enable();
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mdelay(1);
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local_irq_disable();
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}
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#endif
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static inline void check_stack_overflow(void)
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{
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#ifdef CONFIG_DEBUG_STACKOVERFLOW
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long sp;
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sp = __get_SP() & (THREAD_SIZE-1);
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/* check for stack overflow: is there less than 2KB free? */
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if (unlikely(sp < (sizeof(struct thread_info) + 2048))) {
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printk("do_IRQ: stack overflow: %ld\n",
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sp - sizeof(struct thread_info));
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dump_stack();
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}
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#endif
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}
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void __do_irq(struct pt_regs *regs)
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{
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struct irq_desc *desc;
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unsigned int irq;
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irq_enter();
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trace_irq_entry(regs);
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check_stack_overflow();
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/*
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* Query the platform PIC for the interrupt & ack it.
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*
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* This will typically lower the interrupt line to the CPU
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*/
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irq = ppc_md.get_irq();
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/* We can hard enable interrupts now to allow perf interrupts */
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may_hard_irq_enable();
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/* And finally process it */
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if (unlikely(irq == NO_IRQ))
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__get_cpu_var(irq_stat).spurious_irqs++;
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else {
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desc = irq_to_desc(irq);
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if (likely(desc))
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desc->handle_irq(irq, desc);
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}
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trace_irq_exit(regs);
|
|
|
|
irq_exit();
|
|
}
|
|
|
|
void do_IRQ(struct pt_regs *regs)
|
|
{
|
|
struct pt_regs *old_regs = set_irq_regs(regs);
|
|
struct thread_info *curtp, *irqtp, *sirqtp;
|
|
|
|
/* Switch to the irq stack to handle this */
|
|
curtp = current_thread_info();
|
|
irqtp = hardirq_ctx[raw_smp_processor_id()];
|
|
sirqtp = softirq_ctx[raw_smp_processor_id()];
|
|
|
|
/* Already there ? */
|
|
if (unlikely(curtp == irqtp || curtp == sirqtp)) {
|
|
__do_irq(regs);
|
|
set_irq_regs(old_regs);
|
|
return;
|
|
}
|
|
|
|
/* Prepare the thread_info in the irq stack */
|
|
irqtp->task = curtp->task;
|
|
irqtp->flags = 0;
|
|
|
|
/* Copy the preempt_count so that the [soft]irq checks work. */
|
|
irqtp->preempt_count = curtp->preempt_count;
|
|
|
|
/* Switch stack and call */
|
|
call_do_irq(regs, irqtp);
|
|
|
|
/* Restore stack limit */
|
|
irqtp->task = NULL;
|
|
|
|
/* Copy back updates to the thread_info */
|
|
if (irqtp->flags)
|
|
set_bits(irqtp->flags, &curtp->flags);
|
|
|
|
set_irq_regs(old_regs);
|
|
}
|
|
|
|
void __init init_IRQ(void)
|
|
{
|
|
if (ppc_md.init_IRQ)
|
|
ppc_md.init_IRQ();
|
|
|
|
exc_lvl_ctx_init();
|
|
|
|
irq_ctx_init();
|
|
}
|
|
|
|
#if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
|
|
struct thread_info *critirq_ctx[NR_CPUS] __read_mostly;
|
|
struct thread_info *dbgirq_ctx[NR_CPUS] __read_mostly;
|
|
struct thread_info *mcheckirq_ctx[NR_CPUS] __read_mostly;
|
|
|
|
void exc_lvl_ctx_init(void)
|
|
{
|
|
struct thread_info *tp;
|
|
int i, cpu_nr;
|
|
|
|
for_each_possible_cpu(i) {
|
|
#ifdef CONFIG_PPC64
|
|
cpu_nr = i;
|
|
#else
|
|
#ifdef CONFIG_SMP
|
|
cpu_nr = get_hard_smp_processor_id(i);
|
|
#else
|
|
cpu_nr = 0;
|
|
#endif
|
|
#endif
|
|
|
|
memset((void *)critirq_ctx[cpu_nr], 0, THREAD_SIZE);
|
|
tp = critirq_ctx[cpu_nr];
|
|
tp->cpu = cpu_nr;
|
|
tp->preempt_count = 0;
|
|
|
|
#ifdef CONFIG_BOOKE
|
|
memset((void *)dbgirq_ctx[cpu_nr], 0, THREAD_SIZE);
|
|
tp = dbgirq_ctx[cpu_nr];
|
|
tp->cpu = cpu_nr;
|
|
tp->preempt_count = 0;
|
|
|
|
memset((void *)mcheckirq_ctx[cpu_nr], 0, THREAD_SIZE);
|
|
tp = mcheckirq_ctx[cpu_nr];
|
|
tp->cpu = cpu_nr;
|
|
tp->preempt_count = HARDIRQ_OFFSET;
|
|
#endif
|
|
}
|
|
}
|
|
#endif
|
|
|
|
struct thread_info *softirq_ctx[NR_CPUS] __read_mostly;
|
|
struct thread_info *hardirq_ctx[NR_CPUS] __read_mostly;
|
|
|
|
void irq_ctx_init(void)
|
|
{
|
|
struct thread_info *tp;
|
|
int i;
|
|
|
|
for_each_possible_cpu(i) {
|
|
memset((void *)softirq_ctx[i], 0, THREAD_SIZE);
|
|
tp = softirq_ctx[i];
|
|
tp->cpu = i;
|
|
|
|
memset((void *)hardirq_ctx[i], 0, THREAD_SIZE);
|
|
tp = hardirq_ctx[i];
|
|
tp->cpu = i;
|
|
}
|
|
}
|
|
|
|
void do_softirq_own_stack(void)
|
|
{
|
|
struct thread_info *curtp, *irqtp;
|
|
|
|
curtp = current_thread_info();
|
|
irqtp = softirq_ctx[smp_processor_id()];
|
|
irqtp->task = curtp->task;
|
|
irqtp->flags = 0;
|
|
call_do_softirq(irqtp);
|
|
irqtp->task = NULL;
|
|
|
|
/* Set any flag that may have been set on the
|
|
* alternate stack
|
|
*/
|
|
if (irqtp->flags)
|
|
set_bits(irqtp->flags, &curtp->flags);
|
|
}
|
|
|
|
irq_hw_number_t virq_to_hw(unsigned int virq)
|
|
{
|
|
struct irq_data *irq_data = irq_get_irq_data(virq);
|
|
return WARN_ON(!irq_data) ? 0 : irq_data->hwirq;
|
|
}
|
|
EXPORT_SYMBOL_GPL(virq_to_hw);
|
|
|
|
#ifdef CONFIG_SMP
|
|
int irq_choose_cpu(const struct cpumask *mask)
|
|
{
|
|
int cpuid;
|
|
|
|
if (cpumask_equal(mask, cpu_online_mask)) {
|
|
static int irq_rover;
|
|
static DEFINE_RAW_SPINLOCK(irq_rover_lock);
|
|
unsigned long flags;
|
|
|
|
/* Round-robin distribution... */
|
|
do_round_robin:
|
|
raw_spin_lock_irqsave(&irq_rover_lock, flags);
|
|
|
|
irq_rover = cpumask_next(irq_rover, cpu_online_mask);
|
|
if (irq_rover >= nr_cpu_ids)
|
|
irq_rover = cpumask_first(cpu_online_mask);
|
|
|
|
cpuid = irq_rover;
|
|
|
|
raw_spin_unlock_irqrestore(&irq_rover_lock, flags);
|
|
} else {
|
|
cpuid = cpumask_first_and(mask, cpu_online_mask);
|
|
if (cpuid >= nr_cpu_ids)
|
|
goto do_round_robin;
|
|
}
|
|
|
|
return get_hard_smp_processor_id(cpuid);
|
|
}
|
|
#else
|
|
int irq_choose_cpu(const struct cpumask *mask)
|
|
{
|
|
return hard_smp_processor_id();
|
|
}
|
|
#endif
|
|
|
|
int arch_early_irq_init(void)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PPC64
|
|
static int __init setup_noirqdistrib(char *str)
|
|
{
|
|
distribute_irqs = 0;
|
|
return 1;
|
|
}
|
|
|
|
__setup("noirqdistrib", setup_noirqdistrib);
|
|
#endif /* CONFIG_PPC64 */
|