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bccce2ec77
Add dwcmshc specific system-level suspend and resume support. Signed-off-by: Jisheng Zhang <Jisheng.Zhang@synaptics.com> Link: https://lore.kernel.org/r/20200515141926.52e088fe@xhacker.debian Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
228 lines
5.6 KiB
C
228 lines
5.6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Driver for Synopsys DesignWare Cores Mobile Storage Host Controller
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*
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* Copyright (C) 2018 Synaptics Incorporated
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*
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* Author: Jisheng Zhang <jszhang@kernel.org>
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*/
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#include <linux/clk.h>
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#include <linux/dma-mapping.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/sizes.h>
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#include "sdhci-pltfm.h"
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/* DWCMSHC specific Mode Select value */
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#define DWCMSHC_CTRL_HS400 0x7
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#define BOUNDARY_OK(addr, len) \
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((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
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struct dwcmshc_priv {
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struct clk *bus_clk;
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};
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/*
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* If DMA addr spans 128MB boundary, we split the DMA transfer into two
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* so that each DMA transfer doesn't exceed the boundary.
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*/
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static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc,
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dma_addr_t addr, int len, unsigned int cmd)
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{
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int tmplen, offset;
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if (likely(!len || BOUNDARY_OK(addr, len))) {
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sdhci_adma_write_desc(host, desc, addr, len, cmd);
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return;
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}
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offset = addr & (SZ_128M - 1);
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tmplen = SZ_128M - offset;
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sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
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addr += tmplen;
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len -= tmplen;
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sdhci_adma_write_desc(host, desc, addr, len, cmd);
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}
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static void dwcmshc_set_uhs_signaling(struct sdhci_host *host,
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unsigned int timing)
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{
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u16 ctrl_2;
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ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
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/* Select Bus Speed Mode for host */
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ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
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if ((timing == MMC_TIMING_MMC_HS200) ||
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(timing == MMC_TIMING_UHS_SDR104))
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ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
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else if (timing == MMC_TIMING_UHS_SDR12)
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ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
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else if ((timing == MMC_TIMING_UHS_SDR25) ||
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(timing == MMC_TIMING_MMC_HS))
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ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
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else if (timing == MMC_TIMING_UHS_SDR50)
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ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
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else if ((timing == MMC_TIMING_UHS_DDR50) ||
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(timing == MMC_TIMING_MMC_DDR52))
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ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
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else if (timing == MMC_TIMING_MMC_HS400)
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ctrl_2 |= DWCMSHC_CTRL_HS400;
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sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
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}
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static const struct sdhci_ops sdhci_dwcmshc_ops = {
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.set_clock = sdhci_set_clock,
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.set_bus_width = sdhci_set_bus_width,
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.set_uhs_signaling = dwcmshc_set_uhs_signaling,
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.get_max_clock = sdhci_pltfm_clk_get_max_clock,
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.reset = sdhci_reset,
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.adma_write_desc = dwcmshc_adma_write_desc,
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};
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static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = {
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.ops = &sdhci_dwcmshc_ops,
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.quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN,
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};
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static int dwcmshc_probe(struct platform_device *pdev)
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{
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struct sdhci_pltfm_host *pltfm_host;
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struct sdhci_host *host;
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struct dwcmshc_priv *priv;
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int err;
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u32 extra;
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host = sdhci_pltfm_init(pdev, &sdhci_dwcmshc_pdata,
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sizeof(struct dwcmshc_priv));
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if (IS_ERR(host))
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return PTR_ERR(host);
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/*
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* extra adma table cnt for cross 128M boundary handling.
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*/
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extra = DIV_ROUND_UP_ULL(dma_get_required_mask(&pdev->dev), SZ_128M);
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if (extra > SDHCI_MAX_SEGS)
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extra = SDHCI_MAX_SEGS;
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host->adma_table_cnt += extra;
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pltfm_host = sdhci_priv(host);
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priv = sdhci_pltfm_priv(pltfm_host);
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pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
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if (IS_ERR(pltfm_host->clk)) {
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err = PTR_ERR(pltfm_host->clk);
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dev_err(&pdev->dev, "failed to get core clk: %d\n", err);
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goto free_pltfm;
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}
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err = clk_prepare_enable(pltfm_host->clk);
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if (err)
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goto free_pltfm;
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priv->bus_clk = devm_clk_get(&pdev->dev, "bus");
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if (!IS_ERR(priv->bus_clk))
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clk_prepare_enable(priv->bus_clk);
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err = mmc_of_parse(host->mmc);
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if (err)
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goto err_clk;
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sdhci_get_of_property(pdev);
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err = sdhci_add_host(host);
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if (err)
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goto err_clk;
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return 0;
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err_clk:
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clk_disable_unprepare(pltfm_host->clk);
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clk_disable_unprepare(priv->bus_clk);
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free_pltfm:
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sdhci_pltfm_free(pdev);
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return err;
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}
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static int dwcmshc_remove(struct platform_device *pdev)
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{
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struct sdhci_host *host = platform_get_drvdata(pdev);
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
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sdhci_remove_host(host, 0);
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clk_disable_unprepare(pltfm_host->clk);
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clk_disable_unprepare(priv->bus_clk);
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sdhci_pltfm_free(pdev);
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return 0;
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}
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#ifdef CONFIG_PM_SLEEP
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static int dwcmshc_suspend(struct device *dev)
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{
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struct sdhci_host *host = dev_get_drvdata(dev);
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
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int ret;
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ret = sdhci_suspend_host(host);
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if (ret)
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return ret;
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clk_disable_unprepare(pltfm_host->clk);
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if (!IS_ERR(priv->bus_clk))
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clk_disable_unprepare(priv->bus_clk);
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return ret;
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}
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static int dwcmshc_resume(struct device *dev)
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{
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struct sdhci_host *host = dev_get_drvdata(dev);
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host);
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int ret;
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ret = clk_prepare_enable(pltfm_host->clk);
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if (ret)
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return ret;
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if (!IS_ERR(priv->bus_clk)) {
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ret = clk_prepare_enable(priv->bus_clk);
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if (ret)
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return ret;
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}
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return sdhci_resume_host(host);
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}
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#endif
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static SIMPLE_DEV_PM_OPS(dwcmshc_pmops, dwcmshc_suspend, dwcmshc_resume);
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static const struct of_device_id sdhci_dwcmshc_dt_ids[] = {
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{ .compatible = "snps,dwcmshc-sdhci" },
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{}
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};
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MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids);
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static struct platform_driver sdhci_dwcmshc_driver = {
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.driver = {
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.name = "sdhci-dwcmshc",
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.of_match_table = sdhci_dwcmshc_dt_ids,
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.pm = &dwcmshc_pmops,
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},
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.probe = dwcmshc_probe,
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.remove = dwcmshc_remove,
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};
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module_platform_driver(sdhci_dwcmshc_driver);
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MODULE_DESCRIPTION("SDHCI platform driver for Synopsys DWC MSHC");
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MODULE_AUTHOR("Jisheng Zhang <jszhang@kernel.org>");
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MODULE_LICENSE("GPL v2");
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