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c150b809f7
* Support for various vector-accelerated crypto routines. * Hibernation is now enabled for portable kernel builds. * mmap_rnd_bits_max is larger on systems with larger VAs. * Support for fast GUP. * Support for membarrier-based instruction cache synchronization. * Support for the Andes hart-level interrupt controller and PMU. * Some cleanups around unaligned access speed probing and Kconfig settings. * Support for ACPI LPI and CPPC. * Various cleanus related to barriers. * A handful of fixes. -----BEGIN PGP SIGNATURE----- iQJHBAABCAAxFiEEKzw3R0RoQ7JKlDp6LhMZ81+7GIkFAmX9icgTHHBhbG1lckBk YWJiZWx0LmNvbQAKCRAuExnzX7sYib+UD/4xyL6UMixx6A06BVBL9UT4vOrxRvNr JIihG5y5QNMjes9DHWL35mZTMqFtQ0tq94ViWFLmJWloV/8KRVM2C9R9KX7vplf3 M/OwvP106spxgvNHoeQbycgs42RU1t2mpqT7N1iK2hCjqieP3vLn6hsSLXWTAG0L 3gQbQw6XCLC3hPyLq+nbFY2i4faeCmpXWmixoy/IvQ5calZQrRU0LNlP6lcMBhVo uocjG0uGAhrahw2s81jxcMZcxa3AvUCiplapdD5H5v9rBM85SkYJj2Q9SqdSorkb xzuimRnKPI5s47yM3pTfZY0qnQUYHV7PXXuw4WujpCQVQdhaG+Ggq63UUZA61J9t IzZK2zdcfHqICrGTtXImUzRT3dcc3oq+IFq4tTY+rEJm29hrXkAtx+qBm5xtMvax fJz5feJ/iT0u7MDj4Oq24n+Kpl+Olm+MJaZX3m5Ovi/9V6a9iK9HXqxg9/Fs0fMO +J/0kTgd8Vu9CYH7KNWz3uztcO9eMAH3VyzuXuab4BGj1i1Y/9EjpALQi7rDN73S OsYQX6NnzMkBV4dvElJVLXiPlvNlMHZZwdak5CqPb48jaJu6iiIZAuvOrG6/naGP wnQSLVA2WWWoOkl3AJhxfpa11CLhbMl9E2gYm1VtNvASXoSFIxlAq1Yv3sG8yjty 4ZT0rYFJOstYiQ== =3dL5 -----END PGP SIGNATURE----- Merge tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux Pull RISC-V updates from Palmer Dabbelt: - Support for various vector-accelerated crypto routines - Hibernation is now enabled for portable kernel builds - mmap_rnd_bits_max is larger on systems with larger VAs - Support for fast GUP - Support for membarrier-based instruction cache synchronization - Support for the Andes hart-level interrupt controller and PMU - Some cleanups around unaligned access speed probing and Kconfig settings - Support for ACPI LPI and CPPC - Various cleanus related to barriers - A handful of fixes * tag 'riscv-for-linus-6.9-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (66 commits) riscv: Fix syscall wrapper for >word-size arguments crypto: riscv - add vector crypto accelerated AES-CBC-CTS crypto: riscv - parallelize AES-CBC decryption riscv: Only flush the mm icache when setting an exec pte riscv: Use kcalloc() instead of kzalloc() riscv/barrier: Add missing space after ',' riscv/barrier: Consolidate fence definitions riscv/barrier: Define RISCV_FULL_BARRIER riscv/barrier: Define __{mb,rmb,wmb} RISC-V: defconfig: Enable CONFIG_ACPI_CPPC_CPUFREQ cpufreq: Move CPPC configs to common Kconfig and add RISC-V ACPI: RISC-V: Add CPPC driver ACPI: Enable ACPI_PROCESSOR for RISC-V ACPI: RISC-V: Add LPI driver cpuidle: RISC-V: Move few functions to arch/riscv riscv: Introduce set_compat_task() in asm/compat.h riscv: Introduce is_compat_thread() into compat.h riscv: add compile-time test into is_compat_task() riscv: Replace direct thread flag check with is_compat_task() riscv: Improve arch_get_mmap_end() macro ...
678 lines
21 KiB
C
678 lines
21 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Copyright (C) 2010-2017 Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
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*
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* membarrier system call
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*/
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/*
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* For documentation purposes, here are some membarrier ordering
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* scenarios to keep in mind:
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*
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* A) Userspace thread execution after IPI vs membarrier's memory
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* barrier before sending the IPI
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*
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* Userspace variables:
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*
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* int x = 0, y = 0;
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*
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* The memory barrier at the start of membarrier() on CPU0 is necessary in
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* order to enforce the guarantee that any writes occurring on CPU0 before
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* the membarrier() is executed will be visible to any code executing on
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* CPU1 after the IPI-induced memory barrier:
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*
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* CPU0 CPU1
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*
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* x = 1
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* membarrier():
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* a: smp_mb()
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* b: send IPI IPI-induced mb
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* c: smp_mb()
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* r2 = y
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* y = 1
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* barrier()
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* r1 = x
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*
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* BUG_ON(r1 == 0 && r2 == 0)
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*
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* The write to y and load from x by CPU1 are unordered by the hardware,
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* so it's possible to have "r1 = x" reordered before "y = 1" at any
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* point after (b). If the memory barrier at (a) is omitted, then "x = 1"
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* can be reordered after (a) (although not after (c)), so we get r1 == 0
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* and r2 == 0. This violates the guarantee that membarrier() is
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* supposed by provide.
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*
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* The timing of the memory barrier at (a) has to ensure that it executes
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* before the IPI-induced memory barrier on CPU1.
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*
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* B) Userspace thread execution before IPI vs membarrier's memory
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* barrier after completing the IPI
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*
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* Userspace variables:
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*
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* int x = 0, y = 0;
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*
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* The memory barrier at the end of membarrier() on CPU0 is necessary in
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* order to enforce the guarantee that any writes occurring on CPU1 before
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* the membarrier() is executed will be visible to any code executing on
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* CPU0 after the membarrier():
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*
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* CPU0 CPU1
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*
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* x = 1
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* barrier()
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* y = 1
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* r2 = y
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* membarrier():
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* a: smp_mb()
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* b: send IPI IPI-induced mb
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* c: smp_mb()
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* r1 = x
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* BUG_ON(r1 == 0 && r2 == 1)
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*
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* The writes to x and y are unordered by the hardware, so it's possible to
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* have "r2 = 1" even though the write to x doesn't execute until (b). If
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* the memory barrier at (c) is omitted then "r1 = x" can be reordered
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* before (b) (although not before (a)), so we get "r1 = 0". This violates
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* the guarantee that membarrier() is supposed to provide.
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*
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* The timing of the memory barrier at (c) has to ensure that it executes
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* after the IPI-induced memory barrier on CPU1.
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*
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* C) Scheduling userspace thread -> kthread -> userspace thread vs membarrier
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*
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* CPU0 CPU1
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*
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* membarrier():
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* a: smp_mb()
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* d: switch to kthread (includes mb)
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* b: read rq->curr->mm == NULL
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* e: switch to user (includes mb)
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* c: smp_mb()
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*
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* Using the scenario from (A), we can show that (a) needs to be paired
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* with (e). Using the scenario from (B), we can show that (c) needs to
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* be paired with (d).
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*
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* D) exit_mm vs membarrier
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*
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* Two thread groups are created, A and B. Thread group B is created by
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* issuing clone from group A with flag CLONE_VM set, but not CLONE_THREAD.
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* Let's assume we have a single thread within each thread group (Thread A
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* and Thread B). Thread A runs on CPU0, Thread B runs on CPU1.
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*
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* CPU0 CPU1
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*
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* membarrier():
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* a: smp_mb()
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* exit_mm():
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* d: smp_mb()
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* e: current->mm = NULL
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* b: read rq->curr->mm == NULL
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* c: smp_mb()
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*
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* Using scenario (B), we can show that (c) needs to be paired with (d).
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*
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* E) kthread_{use,unuse}_mm vs membarrier
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*
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* CPU0 CPU1
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*
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* membarrier():
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* a: smp_mb()
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* kthread_unuse_mm()
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* d: smp_mb()
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* e: current->mm = NULL
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* b: read rq->curr->mm == NULL
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* kthread_use_mm()
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* f: current->mm = mm
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* g: smp_mb()
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* c: smp_mb()
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*
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* Using the scenario from (A), we can show that (a) needs to be paired
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* with (g). Using the scenario from (B), we can show that (c) needs to
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* be paired with (d).
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*/
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/*
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* Bitmask made from a "or" of all commands within enum membarrier_cmd,
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* except MEMBARRIER_CMD_QUERY.
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*/
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#ifdef CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE
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#define MEMBARRIER_PRIVATE_EXPEDITED_SYNC_CORE_BITMASK \
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(MEMBARRIER_CMD_PRIVATE_EXPEDITED_SYNC_CORE \
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| MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_SYNC_CORE)
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#else
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#define MEMBARRIER_PRIVATE_EXPEDITED_SYNC_CORE_BITMASK 0
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#endif
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#ifdef CONFIG_RSEQ
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#define MEMBARRIER_PRIVATE_EXPEDITED_RSEQ_BITMASK \
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(MEMBARRIER_CMD_PRIVATE_EXPEDITED_RSEQ \
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| MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_RSEQ)
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#else
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#define MEMBARRIER_PRIVATE_EXPEDITED_RSEQ_BITMASK 0
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#endif
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#define MEMBARRIER_CMD_BITMASK \
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(MEMBARRIER_CMD_GLOBAL | MEMBARRIER_CMD_GLOBAL_EXPEDITED \
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| MEMBARRIER_CMD_REGISTER_GLOBAL_EXPEDITED \
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| MEMBARRIER_CMD_PRIVATE_EXPEDITED \
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| MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED \
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| MEMBARRIER_PRIVATE_EXPEDITED_SYNC_CORE_BITMASK \
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| MEMBARRIER_PRIVATE_EXPEDITED_RSEQ_BITMASK \
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| MEMBARRIER_CMD_GET_REGISTRATIONS)
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static DEFINE_MUTEX(membarrier_ipi_mutex);
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#define SERIALIZE_IPI() guard(mutex)(&membarrier_ipi_mutex)
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static void ipi_mb(void *info)
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{
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smp_mb(); /* IPIs should be serializing but paranoid. */
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}
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static void ipi_sync_core(void *info)
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{
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/*
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* The smp_mb() in membarrier after all the IPIs is supposed to
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* ensure that memory on remote CPUs that occur before the IPI
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* become visible to membarrier()'s caller -- see scenario B in
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* the big comment at the top of this file.
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*
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* A sync_core() would provide this guarantee, but
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* sync_core_before_usermode() might end up being deferred until
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* after membarrier()'s smp_mb().
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*/
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smp_mb(); /* IPIs should be serializing but paranoid. */
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sync_core_before_usermode();
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}
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static void ipi_rseq(void *info)
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{
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/*
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* Ensure that all stores done by the calling thread are visible
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* to the current task before the current task resumes. We could
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* probably optimize this away on most architectures, but by the
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* time we've already sent an IPI, the cost of the extra smp_mb()
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* is negligible.
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*/
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smp_mb();
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rseq_preempt(current);
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}
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static void ipi_sync_rq_state(void *info)
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{
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struct mm_struct *mm = (struct mm_struct *) info;
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if (current->mm != mm)
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return;
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this_cpu_write(runqueues.membarrier_state,
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atomic_read(&mm->membarrier_state));
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/*
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* Issue a memory barrier after setting
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* MEMBARRIER_STATE_GLOBAL_EXPEDITED in the current runqueue to
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* guarantee that no memory access following registration is reordered
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* before registration.
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*/
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smp_mb();
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}
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void membarrier_exec_mmap(struct mm_struct *mm)
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{
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/*
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* Issue a memory barrier before clearing membarrier_state to
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* guarantee that no memory access prior to exec is reordered after
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* clearing this state.
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*/
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smp_mb();
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atomic_set(&mm->membarrier_state, 0);
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/*
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* Keep the runqueue membarrier_state in sync with this mm
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* membarrier_state.
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*/
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this_cpu_write(runqueues.membarrier_state, 0);
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}
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void membarrier_update_current_mm(struct mm_struct *next_mm)
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{
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struct rq *rq = this_rq();
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int membarrier_state = 0;
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if (next_mm)
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membarrier_state = atomic_read(&next_mm->membarrier_state);
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if (READ_ONCE(rq->membarrier_state) == membarrier_state)
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return;
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WRITE_ONCE(rq->membarrier_state, membarrier_state);
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}
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static int membarrier_global_expedited(void)
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{
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int cpu;
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cpumask_var_t tmpmask;
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if (num_online_cpus() == 1)
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return 0;
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/*
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* Matches memory barriers after rq->curr modification in
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* scheduler.
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*/
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smp_mb(); /* system call entry is not a mb. */
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if (!zalloc_cpumask_var(&tmpmask, GFP_KERNEL))
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return -ENOMEM;
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SERIALIZE_IPI();
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cpus_read_lock();
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rcu_read_lock();
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for_each_online_cpu(cpu) {
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struct task_struct *p;
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/*
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* Skipping the current CPU is OK even through we can be
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* migrated at any point. The current CPU, at the point
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* where we read raw_smp_processor_id(), is ensured to
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* be in program order with respect to the caller
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* thread. Therefore, we can skip this CPU from the
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* iteration.
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*/
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if (cpu == raw_smp_processor_id())
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continue;
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if (!(READ_ONCE(cpu_rq(cpu)->membarrier_state) &
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MEMBARRIER_STATE_GLOBAL_EXPEDITED))
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continue;
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/*
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* Skip the CPU if it runs a kernel thread which is not using
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* a task mm.
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*/
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p = rcu_dereference(cpu_rq(cpu)->curr);
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if (!p->mm)
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continue;
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__cpumask_set_cpu(cpu, tmpmask);
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}
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rcu_read_unlock();
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preempt_disable();
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smp_call_function_many(tmpmask, ipi_mb, NULL, 1);
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preempt_enable();
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free_cpumask_var(tmpmask);
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cpus_read_unlock();
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/*
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* Memory barrier on the caller thread _after_ we finished
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* waiting for the last IPI. Matches memory barriers before
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* rq->curr modification in scheduler.
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*/
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smp_mb(); /* exit from system call is not a mb */
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return 0;
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}
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static int membarrier_private_expedited(int flags, int cpu_id)
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{
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cpumask_var_t tmpmask;
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struct mm_struct *mm = current->mm;
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smp_call_func_t ipi_func = ipi_mb;
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if (flags == MEMBARRIER_FLAG_SYNC_CORE) {
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if (!IS_ENABLED(CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE))
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return -EINVAL;
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if (!(atomic_read(&mm->membarrier_state) &
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MEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE_READY))
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return -EPERM;
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ipi_func = ipi_sync_core;
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prepare_sync_core_cmd(mm);
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} else if (flags == MEMBARRIER_FLAG_RSEQ) {
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if (!IS_ENABLED(CONFIG_RSEQ))
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return -EINVAL;
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if (!(atomic_read(&mm->membarrier_state) &
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MEMBARRIER_STATE_PRIVATE_EXPEDITED_RSEQ_READY))
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return -EPERM;
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ipi_func = ipi_rseq;
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} else {
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WARN_ON_ONCE(flags);
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if (!(atomic_read(&mm->membarrier_state) &
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MEMBARRIER_STATE_PRIVATE_EXPEDITED_READY))
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return -EPERM;
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}
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if (flags != MEMBARRIER_FLAG_SYNC_CORE &&
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(atomic_read(&mm->mm_users) == 1 || num_online_cpus() == 1))
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return 0;
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/*
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* Matches memory barriers after rq->curr modification in
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* scheduler.
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*
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* On RISC-V, this barrier pairing is also needed for the
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* SYNC_CORE command when switching between processes, cf.
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* the inline comments in membarrier_arch_switch_mm().
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*/
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smp_mb(); /* system call entry is not a mb. */
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if (cpu_id < 0 && !zalloc_cpumask_var(&tmpmask, GFP_KERNEL))
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return -ENOMEM;
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SERIALIZE_IPI();
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cpus_read_lock();
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if (cpu_id >= 0) {
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struct task_struct *p;
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if (cpu_id >= nr_cpu_ids || !cpu_online(cpu_id))
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goto out;
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rcu_read_lock();
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p = rcu_dereference(cpu_rq(cpu_id)->curr);
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if (!p || p->mm != mm) {
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rcu_read_unlock();
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goto out;
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}
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rcu_read_unlock();
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} else {
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int cpu;
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rcu_read_lock();
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for_each_online_cpu(cpu) {
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struct task_struct *p;
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p = rcu_dereference(cpu_rq(cpu)->curr);
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if (p && p->mm == mm)
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__cpumask_set_cpu(cpu, tmpmask);
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}
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rcu_read_unlock();
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}
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if (cpu_id >= 0) {
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/*
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* smp_call_function_single() will call ipi_func() if cpu_id
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* is the calling CPU.
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*/
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smp_call_function_single(cpu_id, ipi_func, NULL, 1);
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} else {
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/*
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* For regular membarrier, we can save a few cycles by
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* skipping the current cpu -- we're about to do smp_mb()
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* below, and if we migrate to a different cpu, this cpu
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* and the new cpu will execute a full barrier in the
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* scheduler.
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*
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* For SYNC_CORE, we do need a barrier on the current cpu --
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* otherwise, if we are migrated and replaced by a different
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* task in the same mm just before, during, or after
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* membarrier, we will end up with some thread in the mm
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* running without a core sync.
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*
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* For RSEQ, don't rseq_preempt() the caller. User code
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* is not supposed to issue syscalls at all from inside an
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* rseq critical section.
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*/
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if (flags != MEMBARRIER_FLAG_SYNC_CORE) {
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preempt_disable();
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smp_call_function_many(tmpmask, ipi_func, NULL, true);
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preempt_enable();
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} else {
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on_each_cpu_mask(tmpmask, ipi_func, NULL, true);
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}
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}
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out:
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if (cpu_id < 0)
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|
free_cpumask_var(tmpmask);
|
|
cpus_read_unlock();
|
|
|
|
/*
|
|
* Memory barrier on the caller thread _after_ we finished
|
|
* waiting for the last IPI. Matches memory barriers before
|
|
* rq->curr modification in scheduler.
|
|
*/
|
|
smp_mb(); /* exit from system call is not a mb */
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int sync_runqueues_membarrier_state(struct mm_struct *mm)
|
|
{
|
|
int membarrier_state = atomic_read(&mm->membarrier_state);
|
|
cpumask_var_t tmpmask;
|
|
int cpu;
|
|
|
|
if (atomic_read(&mm->mm_users) == 1 || num_online_cpus() == 1) {
|
|
this_cpu_write(runqueues.membarrier_state, membarrier_state);
|
|
|
|
/*
|
|
* For single mm user, we can simply issue a memory barrier
|
|
* after setting MEMBARRIER_STATE_GLOBAL_EXPEDITED in the
|
|
* mm and in the current runqueue to guarantee that no memory
|
|
* access following registration is reordered before
|
|
* registration.
|
|
*/
|
|
smp_mb();
|
|
return 0;
|
|
}
|
|
|
|
if (!zalloc_cpumask_var(&tmpmask, GFP_KERNEL))
|
|
return -ENOMEM;
|
|
|
|
/*
|
|
* For mm with multiple users, we need to ensure all future
|
|
* scheduler executions will observe @mm's new membarrier
|
|
* state.
|
|
*/
|
|
synchronize_rcu();
|
|
|
|
/*
|
|
* For each cpu runqueue, if the task's mm match @mm, ensure that all
|
|
* @mm's membarrier state set bits are also set in the runqueue's
|
|
* membarrier state. This ensures that a runqueue scheduling
|
|
* between threads which are users of @mm has its membarrier state
|
|
* updated.
|
|
*/
|
|
SERIALIZE_IPI();
|
|
cpus_read_lock();
|
|
rcu_read_lock();
|
|
for_each_online_cpu(cpu) {
|
|
struct rq *rq = cpu_rq(cpu);
|
|
struct task_struct *p;
|
|
|
|
p = rcu_dereference(rq->curr);
|
|
if (p && p->mm == mm)
|
|
__cpumask_set_cpu(cpu, tmpmask);
|
|
}
|
|
rcu_read_unlock();
|
|
|
|
on_each_cpu_mask(tmpmask, ipi_sync_rq_state, mm, true);
|
|
|
|
free_cpumask_var(tmpmask);
|
|
cpus_read_unlock();
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int membarrier_register_global_expedited(void)
|
|
{
|
|
struct task_struct *p = current;
|
|
struct mm_struct *mm = p->mm;
|
|
int ret;
|
|
|
|
if (atomic_read(&mm->membarrier_state) &
|
|
MEMBARRIER_STATE_GLOBAL_EXPEDITED_READY)
|
|
return 0;
|
|
atomic_or(MEMBARRIER_STATE_GLOBAL_EXPEDITED, &mm->membarrier_state);
|
|
ret = sync_runqueues_membarrier_state(mm);
|
|
if (ret)
|
|
return ret;
|
|
atomic_or(MEMBARRIER_STATE_GLOBAL_EXPEDITED_READY,
|
|
&mm->membarrier_state);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int membarrier_register_private_expedited(int flags)
|
|
{
|
|
struct task_struct *p = current;
|
|
struct mm_struct *mm = p->mm;
|
|
int ready_state = MEMBARRIER_STATE_PRIVATE_EXPEDITED_READY,
|
|
set_state = MEMBARRIER_STATE_PRIVATE_EXPEDITED,
|
|
ret;
|
|
|
|
if (flags == MEMBARRIER_FLAG_SYNC_CORE) {
|
|
if (!IS_ENABLED(CONFIG_ARCH_HAS_MEMBARRIER_SYNC_CORE))
|
|
return -EINVAL;
|
|
ready_state =
|
|
MEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE_READY;
|
|
} else if (flags == MEMBARRIER_FLAG_RSEQ) {
|
|
if (!IS_ENABLED(CONFIG_RSEQ))
|
|
return -EINVAL;
|
|
ready_state =
|
|
MEMBARRIER_STATE_PRIVATE_EXPEDITED_RSEQ_READY;
|
|
} else {
|
|
WARN_ON_ONCE(flags);
|
|
}
|
|
|
|
/*
|
|
* We need to consider threads belonging to different thread
|
|
* groups, which use the same mm. (CLONE_VM but not
|
|
* CLONE_THREAD).
|
|
*/
|
|
if ((atomic_read(&mm->membarrier_state) & ready_state) == ready_state)
|
|
return 0;
|
|
if (flags & MEMBARRIER_FLAG_SYNC_CORE)
|
|
set_state |= MEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE;
|
|
if (flags & MEMBARRIER_FLAG_RSEQ)
|
|
set_state |= MEMBARRIER_STATE_PRIVATE_EXPEDITED_RSEQ;
|
|
atomic_or(set_state, &mm->membarrier_state);
|
|
ret = sync_runqueues_membarrier_state(mm);
|
|
if (ret)
|
|
return ret;
|
|
atomic_or(ready_state, &mm->membarrier_state);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int membarrier_get_registrations(void)
|
|
{
|
|
struct task_struct *p = current;
|
|
struct mm_struct *mm = p->mm;
|
|
int registrations_mask = 0, membarrier_state, i;
|
|
static const int states[] = {
|
|
MEMBARRIER_STATE_GLOBAL_EXPEDITED |
|
|
MEMBARRIER_STATE_GLOBAL_EXPEDITED_READY,
|
|
MEMBARRIER_STATE_PRIVATE_EXPEDITED |
|
|
MEMBARRIER_STATE_PRIVATE_EXPEDITED_READY,
|
|
MEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE |
|
|
MEMBARRIER_STATE_PRIVATE_EXPEDITED_SYNC_CORE_READY,
|
|
MEMBARRIER_STATE_PRIVATE_EXPEDITED_RSEQ |
|
|
MEMBARRIER_STATE_PRIVATE_EXPEDITED_RSEQ_READY
|
|
};
|
|
static const int registration_cmds[] = {
|
|
MEMBARRIER_CMD_REGISTER_GLOBAL_EXPEDITED,
|
|
MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED,
|
|
MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_SYNC_CORE,
|
|
MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_RSEQ
|
|
};
|
|
BUILD_BUG_ON(ARRAY_SIZE(states) != ARRAY_SIZE(registration_cmds));
|
|
|
|
membarrier_state = atomic_read(&mm->membarrier_state);
|
|
for (i = 0; i < ARRAY_SIZE(states); ++i) {
|
|
if (membarrier_state & states[i]) {
|
|
registrations_mask |= registration_cmds[i];
|
|
membarrier_state &= ~states[i];
|
|
}
|
|
}
|
|
WARN_ON_ONCE(membarrier_state != 0);
|
|
return registrations_mask;
|
|
}
|
|
|
|
/**
|
|
* sys_membarrier - issue memory barriers on a set of threads
|
|
* @cmd: Takes command values defined in enum membarrier_cmd.
|
|
* @flags: Currently needs to be 0 for all commands other than
|
|
* MEMBARRIER_CMD_PRIVATE_EXPEDITED_RSEQ: in the latter
|
|
* case it can be MEMBARRIER_CMD_FLAG_CPU, indicating that @cpu_id
|
|
* contains the CPU on which to interrupt (= restart)
|
|
* the RSEQ critical section.
|
|
* @cpu_id: if @flags == MEMBARRIER_CMD_FLAG_CPU, indicates the cpu on which
|
|
* RSEQ CS should be interrupted (@cmd must be
|
|
* MEMBARRIER_CMD_PRIVATE_EXPEDITED_RSEQ).
|
|
*
|
|
* If this system call is not implemented, -ENOSYS is returned. If the
|
|
* command specified does not exist, not available on the running
|
|
* kernel, or if the command argument is invalid, this system call
|
|
* returns -EINVAL. For a given command, with flags argument set to 0,
|
|
* if this system call returns -ENOSYS or -EINVAL, it is guaranteed to
|
|
* always return the same value until reboot. In addition, it can return
|
|
* -ENOMEM if there is not enough memory available to perform the system
|
|
* call.
|
|
*
|
|
* All memory accesses performed in program order from each targeted thread
|
|
* is guaranteed to be ordered with respect to sys_membarrier(). If we use
|
|
* the semantic "barrier()" to represent a compiler barrier forcing memory
|
|
* accesses to be performed in program order across the barrier, and
|
|
* smp_mb() to represent explicit memory barriers forcing full memory
|
|
* ordering across the barrier, we have the following ordering table for
|
|
* each pair of barrier(), sys_membarrier() and smp_mb():
|
|
*
|
|
* The pair ordering is detailed as (O: ordered, X: not ordered):
|
|
*
|
|
* barrier() smp_mb() sys_membarrier()
|
|
* barrier() X X O
|
|
* smp_mb() X O O
|
|
* sys_membarrier() O O O
|
|
*/
|
|
SYSCALL_DEFINE3(membarrier, int, cmd, unsigned int, flags, int, cpu_id)
|
|
{
|
|
switch (cmd) {
|
|
case MEMBARRIER_CMD_PRIVATE_EXPEDITED_RSEQ:
|
|
if (unlikely(flags && flags != MEMBARRIER_CMD_FLAG_CPU))
|
|
return -EINVAL;
|
|
break;
|
|
default:
|
|
if (unlikely(flags))
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (!(flags & MEMBARRIER_CMD_FLAG_CPU))
|
|
cpu_id = -1;
|
|
|
|
switch (cmd) {
|
|
case MEMBARRIER_CMD_QUERY:
|
|
{
|
|
int cmd_mask = MEMBARRIER_CMD_BITMASK;
|
|
|
|
if (tick_nohz_full_enabled())
|
|
cmd_mask &= ~MEMBARRIER_CMD_GLOBAL;
|
|
return cmd_mask;
|
|
}
|
|
case MEMBARRIER_CMD_GLOBAL:
|
|
/* MEMBARRIER_CMD_GLOBAL is not compatible with nohz_full. */
|
|
if (tick_nohz_full_enabled())
|
|
return -EINVAL;
|
|
if (num_online_cpus() > 1)
|
|
synchronize_rcu();
|
|
return 0;
|
|
case MEMBARRIER_CMD_GLOBAL_EXPEDITED:
|
|
return membarrier_global_expedited();
|
|
case MEMBARRIER_CMD_REGISTER_GLOBAL_EXPEDITED:
|
|
return membarrier_register_global_expedited();
|
|
case MEMBARRIER_CMD_PRIVATE_EXPEDITED:
|
|
return membarrier_private_expedited(0, cpu_id);
|
|
case MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED:
|
|
return membarrier_register_private_expedited(0);
|
|
case MEMBARRIER_CMD_PRIVATE_EXPEDITED_SYNC_CORE:
|
|
return membarrier_private_expedited(MEMBARRIER_FLAG_SYNC_CORE, cpu_id);
|
|
case MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_SYNC_CORE:
|
|
return membarrier_register_private_expedited(MEMBARRIER_FLAG_SYNC_CORE);
|
|
case MEMBARRIER_CMD_PRIVATE_EXPEDITED_RSEQ:
|
|
return membarrier_private_expedited(MEMBARRIER_FLAG_RSEQ, cpu_id);
|
|
case MEMBARRIER_CMD_REGISTER_PRIVATE_EXPEDITED_RSEQ:
|
|
return membarrier_register_private_expedited(MEMBARRIER_FLAG_RSEQ);
|
|
case MEMBARRIER_CMD_GET_REGISTRATIONS:
|
|
return membarrier_get_registrations();
|
|
default:
|
|
return -EINVAL;
|
|
}
|
|
}
|