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ef2b1d777d
The atlas7 clock controller driver registers a reset controller
for itself, which causes a link error when the subsystem is
disabled:
drivers/built-in.o: In function `atlas7_clk_init':
drivers/clk/sirf/clk-atlas7.c:1681: undefined reference to `reset_controller_register'
As the clk driver does not have a Kconfig symbol for itself
but it always built-in when the platform is enabled, we have
to ensure that the reset controller subsystem is also built-in
in this case.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Fixes: 301c5d2940 ("clk: sirf: add CSR atlas7 clk and reset support")
48 lines
972 B
Plaintext
48 lines
972 B
Plaintext
menuconfig ARCH_SIRF
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bool "CSR SiRF"
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depends on ARCH_MULTI_V7
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select ARCH_HAS_RESET_CONTROLLER
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select RESET_CONTROLLER
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select ARCH_REQUIRE_GPIOLIB
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select GENERIC_IRQ_CHIP
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select NO_IOPORT_MAP
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select REGMAP
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select PINCTRL
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select PINCTRL_SIRF
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help
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Support for CSR SiRFprimaII/Marco/Polo platforms
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if ARCH_SIRF
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comment "CSR SiRF atlas6/primaII/Atlas7 Specific Features"
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config ARCH_ATLAS6
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bool "CSR SiRFSoC ATLAS6 ARM Cortex A9 Platform"
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default y
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select SIRF_IRQ
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help
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Support for CSR SiRFSoC ARM Cortex A9 Platform
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config ARCH_ATLAS7
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bool "CSR SiRFSoC ATLAS7 ARM Cortex A7 Platform"
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default y
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select ARM_GIC
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select CPU_V7
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select HAVE_ARM_SCU if SMP
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select HAVE_SMP
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help
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Support for CSR SiRFSoC ARM Cortex A7 Platform
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config ARCH_PRIMA2
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bool "CSR SiRFSoC PRIMA2 ARM Cortex A9 Platform"
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default y
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select SIRF_IRQ
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select ZONE_DMA
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help
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Support for CSR SiRFSoC ARM Cortex A9 Platform
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config SIRF_IRQ
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bool
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endif
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