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Xilinx platforms have no hardwired video capture or video processing interface. Users create capture and memory to memory processing pipelines in the FPGA fabric to suit their particular needs, by instantiating video IP cores from a large library. The Xilinx Video IP core is a framework that models a video pipeline described in the device tree and expose the pipeline to userspace through the media controller and V4L2 APIs. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Hans Verkuil <hans.verkuil@cisco.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@osg.samsung.com>
50 lines
1.4 KiB
C
50 lines
1.4 KiB
C
/*
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* Xilinx Video IP Composite Device
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*
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* Copyright (C) 2013-2015 Ideas on Board
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* Copyright (C) 2013-2015 Xilinx, Inc.
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*
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* Contacts: Hyun Kwon <hyun.kwon@xilinx.com>
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* Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __XILINX_VIPP_H__
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#define __XILINX_VIPP_H__
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#include <linux/list.h>
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#include <linux/mutex.h>
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#include <media/media-device.h>
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#include <media/v4l2-async.h>
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#include <media/v4l2-ctrls.h>
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#include <media/v4l2-device.h>
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/**
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* struct xvip_composite_device - Xilinx Video IP device structure
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* @v4l2_dev: V4L2 device
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* @media_dev: media device
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* @dev: (OF) device
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* @notifier: V4L2 asynchronous subdevs notifier
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* @entities: entities in the graph as a list of xvip_graph_entity
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* @num_subdevs: number of subdevs in the pipeline
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* @dmas: list of DMA channels at the pipeline output and input
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* @v4l2_caps: V4L2 capabilities of the whole device (see VIDIOC_QUERYCAP)
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*/
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struct xvip_composite_device {
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struct v4l2_device v4l2_dev;
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struct media_device media_dev;
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struct device *dev;
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struct v4l2_async_notifier notifier;
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struct list_head entities;
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unsigned int num_subdevs;
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struct list_head dmas;
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u32 v4l2_caps;
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};
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#endif /* __XILINX_VIPP_H__ */
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