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f3b8172fe1
At the end of a trace collection, we try to clear the entire buffer
and enable the ETR back if it was already enabled. But, we would have
adjusted the drvdata->buf to point to the beginning of the trace data
in the trace buffer @drvdata->vaddr. So, the following code which
clears the buffer is dangerous and can cause crashes, like below :
memset(drvdata->buf, 0, drvdata->size);
Unable to handle kernel paging request at virtual address ffffff800a145000
pgd = ffffffc974726000
*pgd=00000009f3e91003, *pud=00000009f3e91003, *pmd=0000000000000000
PREEMPT SMP
Modules linked in:
CPU: 4 PID: 1692 Comm: dd Not tainted 4.7.0-rc2+ #1721
Hardware name: ARM Juno development board (r0) (DT)
task: ffffffc9734a0080 ti: ffffffc974460000 task.ti: ffffffc974460000
PC is at __memset+0x1ac/0x200
LR is at tmc_read_unprepare_etr+0x144/0x1bc
pc : [<ffffff80083a05ac>] lr : [<ffffff800859c984>] pstate: 200001c5
...
[<ffffff80083a05ac>] __memset+0x1ac/0x200
[<ffffff800859b2e4>] tmc_release+0x90/0x94
[<ffffff8008202f58>] __fput+0xa8/0x1ec
[<ffffff80082030f4>] ____fput+0xc/0x14
[<ffffff80080c3ef8>] task_work_run+0xb0/0xe4
[<ffffff8008088bf4>] do_notify_resume+0x64/0x6c
[<ffffff8008084d5c>] work_pending+0x10/0x14
Code: 91010108 54ffff4a 8b040108 cb050042 (d50b7428)
Since we clear the buffer anyway in the following call to
tmc_etr_enable_hw(), remove the erroneous memset().
Fixes: commit
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|---|---|---|
| .. | ||
| coresight-etb10.c | ||
| coresight-etm3x-sysfs.c | ||
| coresight-etm3x.c | ||
| coresight-etm4x-sysfs.c | ||
| coresight-etm4x.c | ||
| coresight-etm4x.h | ||
| coresight-etm-cp14.c | ||
| coresight-etm-perf.c | ||
| coresight-etm-perf.h | ||
| coresight-etm.h | ||
| coresight-funnel.c | ||
| coresight-priv.h | ||
| coresight-replicator-qcom.c | ||
| coresight-replicator.c | ||
| coresight-stm.c | ||
| coresight-tmc-etf.c | ||
| coresight-tmc-etr.c | ||
| coresight-tmc.c | ||
| coresight-tmc.h | ||
| coresight-tpiu.c | ||
| coresight.c | ||
| Kconfig | ||
| Makefile | ||
| of_coresight.c | ||