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1fe56dc16a
This patch add registers, bit fields and compatible strings for Exynos3250 TMU (Thermal Management Unit). Exynos3250 uses the Cortex-A7 dual cores and has a target speed of 1.0 GHz. Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> [Add MUX address setting bits by Jonghwa Lee] Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Reviewed-by: Amit Daniel Kachhap<amit.daniel@samsung.com> Signed-off-by: Zhang Rui <rui.zhang@intel.com>
549 lines
18 KiB
C
549 lines
18 KiB
C
/*
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* exynos_tmu_data.c - Samsung EXYNOS tmu data file
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*
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* Copyright (C) 2013 Samsung Electronics
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* Amit Daniel Kachhap <amit.daniel@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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*/
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#include "exynos_thermal_common.h"
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#include "exynos_tmu.h"
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#include "exynos_tmu_data.h"
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#if defined(CONFIG_CPU_EXYNOS4210)
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static const struct exynos_tmu_registers exynos4210_tmu_registers = {
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.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
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.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
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.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
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.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
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.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
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.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
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.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
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.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
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.tmu_status = EXYNOS_TMU_REG_STATUS,
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.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
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.threshold_temp = EXYNOS4210_TMU_REG_THRESHOLD_TEMP,
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.threshold_th0 = EXYNOS4210_TMU_REG_TRIG_LEVEL0,
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.tmu_inten = EXYNOS_TMU_REG_INTEN,
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.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
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.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
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.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
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.inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
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.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
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.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
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.intclr_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
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};
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struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
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.tmu_data = {
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{
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.threshold = 80,
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.trigger_levels[0] = 5,
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.trigger_levels[1] = 20,
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.trigger_levels[2] = 30,
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.trigger_enable[0] = true,
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.trigger_enable[1] = true,
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.trigger_enable[2] = true,
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.trigger_enable[3] = false,
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.trigger_type[0] = THROTTLE_ACTIVE,
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.trigger_type[1] = THROTTLE_ACTIVE,
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.trigger_type[2] = SW_TRIP,
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.max_trigger_level = 4,
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.gain = 15,
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.reference_voltage = 7,
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.cal_type = TYPE_ONE_POINT_TRIMMING,
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.min_efuse_value = 40,
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.max_efuse_value = 100,
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.first_point_trim = 25,
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.second_point_trim = 85,
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.default_temp_offset = 50,
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.freq_tab[0] = {
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.freq_clip_max = 800 * 1000,
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.temp_level = 85,
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},
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.freq_tab[1] = {
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.freq_clip_max = 200 * 1000,
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.temp_level = 100,
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},
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.freq_tab_count = 2,
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.type = SOC_ARCH_EXYNOS4210,
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.registers = &exynos4210_tmu_registers,
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.features = TMU_SUPPORT_READY_STATUS,
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},
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},
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.tmu_count = 1,
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};
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#endif
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#if defined(CONFIG_SOC_EXYNOS3250)
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static const struct exynos_tmu_registers exynos3250_tmu_registers = {
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.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
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.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
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.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
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.test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT,
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.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
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.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
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.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
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.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
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.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
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.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
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.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
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.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
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.tmu_status = EXYNOS_TMU_REG_STATUS,
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.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
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.threshold_th0 = EXYNOS_THD_TEMP_RISE,
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.threshold_th1 = EXYNOS_THD_TEMP_FALL,
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.tmu_inten = EXYNOS_TMU_REG_INTEN,
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.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
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.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
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.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
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.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
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.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
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.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
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.intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
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.intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
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.intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
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.intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
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.emul_con = EXYNOS_EMUL_CON,
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.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
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.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
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.emul_time_mask = EXYNOS_EMUL_TIME_MASK,
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};
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#define EXYNOS3250_TMU_DATA \
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.threshold_falling = 10, \
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.trigger_levels[0] = 70, \
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.trigger_levels[1] = 95, \
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.trigger_levels[2] = 110, \
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.trigger_levels[3] = 120, \
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.trigger_enable[0] = true, \
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.trigger_enable[1] = true, \
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.trigger_enable[2] = true, \
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.trigger_enable[3] = false, \
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.trigger_type[0] = THROTTLE_ACTIVE, \
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.trigger_type[1] = THROTTLE_ACTIVE, \
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.trigger_type[2] = SW_TRIP, \
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.trigger_type[3] = HW_TRIP, \
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.max_trigger_level = 4, \
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.gain = 8, \
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.reference_voltage = 16, \
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.noise_cancel_mode = 4, \
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.cal_type = TYPE_TWO_POINT_TRIMMING, \
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.efuse_value = 55, \
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.min_efuse_value = 40, \
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.max_efuse_value = 100, \
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.first_point_trim = 25, \
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.second_point_trim = 85, \
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.default_temp_offset = 50, \
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.freq_tab[0] = { \
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.freq_clip_max = 800 * 1000, \
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.temp_level = 70, \
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}, \
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.freq_tab[1] = { \
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.freq_clip_max = 400 * 1000, \
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.temp_level = 95, \
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}, \
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.freq_tab_count = 2, \
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.registers = &exynos3250_tmu_registers, \
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.features = (TMU_SUPPORT_EMULATION | \
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TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
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TMU_SUPPORT_EMUL_TIME)
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#endif
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#if defined(CONFIG_SOC_EXYNOS3250)
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struct exynos_tmu_init_data const exynos3250_default_tmu_data = {
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.tmu_data = {
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{
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EXYNOS3250_TMU_DATA,
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.type = SOC_ARCH_EXYNOS3250,
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.test_mux = EXYNOS4412_MUX_ADDR_VALUE,
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},
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},
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.tmu_count = 1,
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};
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#endif
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#if defined(CONFIG_SOC_EXYNOS4412) || defined(CONFIG_SOC_EXYNOS5250)
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static const struct exynos_tmu_registers exynos4412_tmu_registers = {
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.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
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.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
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.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
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.triminfo_ctrl = EXYNOS_TMU_TRIMINFO_CON,
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.triminfo_reload_shift = EXYNOS_TRIMINFO_RELOAD_SHIFT,
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
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.test_mux_addr_shift = EXYNOS4412_MUX_ADDR_SHIFT,
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.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
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.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
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.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
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.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
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.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
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.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
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.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
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.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
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.tmu_status = EXYNOS_TMU_REG_STATUS,
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.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
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.threshold_th0 = EXYNOS_THD_TEMP_RISE,
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.threshold_th1 = EXYNOS_THD_TEMP_FALL,
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.tmu_inten = EXYNOS_TMU_REG_INTEN,
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.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
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.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
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.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
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.inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
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.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
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.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
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.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
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.intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
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.intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
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.intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
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.intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
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.emul_con = EXYNOS_EMUL_CON,
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.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
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.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
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.emul_time_mask = EXYNOS_EMUL_TIME_MASK,
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};
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#define EXYNOS4412_TMU_DATA \
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.threshold_falling = 10, \
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.trigger_levels[0] = 70, \
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.trigger_levels[1] = 95, \
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.trigger_levels[2] = 110, \
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.trigger_levels[3] = 120, \
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.trigger_enable[0] = true, \
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.trigger_enable[1] = true, \
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.trigger_enable[2] = true, \
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.trigger_enable[3] = false, \
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.trigger_type[0] = THROTTLE_ACTIVE, \
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.trigger_type[1] = THROTTLE_ACTIVE, \
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.trigger_type[2] = SW_TRIP, \
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.trigger_type[3] = HW_TRIP, \
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.max_trigger_level = 4, \
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.gain = 8, \
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.reference_voltage = 16, \
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.noise_cancel_mode = 4, \
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.cal_type = TYPE_ONE_POINT_TRIMMING, \
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.efuse_value = 55, \
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.min_efuse_value = 40, \
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.max_efuse_value = 100, \
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.first_point_trim = 25, \
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.second_point_trim = 85, \
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.default_temp_offset = 50, \
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.freq_tab[0] = { \
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.freq_clip_max = 1400 * 1000, \
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.temp_level = 70, \
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}, \
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.freq_tab[1] = { \
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.freq_clip_max = 400 * 1000, \
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.temp_level = 95, \
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}, \
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.freq_tab_count = 2, \
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.registers = &exynos4412_tmu_registers, \
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.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
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TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
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TMU_SUPPORT_EMUL_TIME)
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#endif
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#if defined(CONFIG_SOC_EXYNOS4412)
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struct exynos_tmu_init_data const exynos4412_default_tmu_data = {
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.tmu_data = {
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{
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EXYNOS4412_TMU_DATA,
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.type = SOC_ARCH_EXYNOS4412,
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.test_mux = EXYNOS4412_MUX_ADDR_VALUE,
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},
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},
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.tmu_count = 1,
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};
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#endif
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#if defined(CONFIG_SOC_EXYNOS5250)
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struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
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.tmu_data = {
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{
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EXYNOS4412_TMU_DATA,
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.type = SOC_ARCH_EXYNOS5250,
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},
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},
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.tmu_count = 1,
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};
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#endif
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#if defined(CONFIG_SOC_EXYNOS5260)
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static const struct exynos_tmu_registers exynos5260_tmu_registers = {
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.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
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.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
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.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL1,
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.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
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.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
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.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
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.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
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.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
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.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
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.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
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.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
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.tmu_status = EXYNOS_TMU_REG_STATUS,
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.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
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.threshold_th0 = EXYNOS_THD_TEMP_RISE,
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.threshold_th1 = EXYNOS_THD_TEMP_FALL,
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.tmu_inten = EXYNOS5260_TMU_REG_INTEN,
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.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
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.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
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.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
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.inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
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.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
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.tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT,
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.tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR,
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.intclr_fall_shift = EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT,
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.intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
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.intclr_rise_mask = EXYNOS5260_TMU_RISE_INT_MASK,
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.intclr_fall_mask = EXYNOS5260_TMU_FALL_INT_MASK,
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.emul_con = EXYNOS5260_EMUL_CON,
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.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
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.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
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.emul_time_mask = EXYNOS_EMUL_TIME_MASK,
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};
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#define __EXYNOS5260_TMU_DATA \
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.threshold_falling = 10, \
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.trigger_levels[0] = 85, \
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.trigger_levels[1] = 103, \
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.trigger_levels[2] = 110, \
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.trigger_levels[3] = 120, \
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.trigger_enable[0] = true, \
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.trigger_enable[1] = true, \
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.trigger_enable[2] = true, \
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.trigger_enable[3] = false, \
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.trigger_type[0] = THROTTLE_ACTIVE, \
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.trigger_type[1] = THROTTLE_ACTIVE, \
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.trigger_type[2] = SW_TRIP, \
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.trigger_type[3] = HW_TRIP, \
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.max_trigger_level = 4, \
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.gain = 8, \
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.reference_voltage = 16, \
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.noise_cancel_mode = 4, \
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.cal_type = TYPE_ONE_POINT_TRIMMING, \
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.efuse_value = 55, \
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.min_efuse_value = 40, \
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.max_efuse_value = 100, \
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.first_point_trim = 25, \
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.second_point_trim = 85, \
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.default_temp_offset = 50, \
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.freq_tab[0] = { \
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.freq_clip_max = 800 * 1000, \
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.temp_level = 85, \
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}, \
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.freq_tab[1] = { \
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.freq_clip_max = 200 * 1000, \
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.temp_level = 103, \
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}, \
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.freq_tab_count = 2, \
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.registers = &exynos5260_tmu_registers, \
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#define EXYNOS5260_TMU_DATA \
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__EXYNOS5260_TMU_DATA \
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.type = SOC_ARCH_EXYNOS5260, \
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.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
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TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
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TMU_SUPPORT_EMUL_TIME)
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struct exynos_tmu_init_data const exynos5260_default_tmu_data = {
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.tmu_data = {
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{ EXYNOS5260_TMU_DATA },
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{ EXYNOS5260_TMU_DATA },
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{ EXYNOS5260_TMU_DATA },
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{ EXYNOS5260_TMU_DATA },
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{ EXYNOS5260_TMU_DATA },
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},
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.tmu_count = 5,
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};
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#endif
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#if defined(CONFIG_SOC_EXYNOS5420)
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static const struct exynos_tmu_registers exynos5420_tmu_registers = {
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.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
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.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
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.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
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.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
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.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
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.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
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.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
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.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
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.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
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.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
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.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
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.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
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.tmu_status = EXYNOS_TMU_REG_STATUS,
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.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
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.threshold_th0 = EXYNOS_THD_TEMP_RISE,
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.threshold_th1 = EXYNOS_THD_TEMP_FALL,
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.tmu_inten = EXYNOS_TMU_REG_INTEN,
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.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
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.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
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.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
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/* INTEN_RISE3 Not availble in exynos5420 */
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.inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
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.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
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.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
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.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
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.intclr_fall_shift = EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT,
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.intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
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.intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
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.intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
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.emul_con = EXYNOS_EMUL_CON,
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.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
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.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
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.emul_time_mask = EXYNOS_EMUL_TIME_MASK,
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};
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|
|
|
#define __EXYNOS5420_TMU_DATA \
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.threshold_falling = 10, \
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|
.trigger_levels[0] = 85, \
|
|
.trigger_levels[1] = 103, \
|
|
.trigger_levels[2] = 110, \
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|
.trigger_levels[3] = 120, \
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|
.trigger_enable[0] = true, \
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|
.trigger_enable[1] = true, \
|
|
.trigger_enable[2] = true, \
|
|
.trigger_enable[3] = false, \
|
|
.trigger_type[0] = THROTTLE_ACTIVE, \
|
|
.trigger_type[1] = THROTTLE_ACTIVE, \
|
|
.trigger_type[2] = SW_TRIP, \
|
|
.trigger_type[3] = HW_TRIP, \
|
|
.max_trigger_level = 4, \
|
|
.gain = 8, \
|
|
.reference_voltage = 16, \
|
|
.noise_cancel_mode = 4, \
|
|
.cal_type = TYPE_ONE_POINT_TRIMMING, \
|
|
.efuse_value = 55, \
|
|
.min_efuse_value = 40, \
|
|
.max_efuse_value = 100, \
|
|
.first_point_trim = 25, \
|
|
.second_point_trim = 85, \
|
|
.default_temp_offset = 50, \
|
|
.freq_tab[0] = { \
|
|
.freq_clip_max = 800 * 1000, \
|
|
.temp_level = 85, \
|
|
}, \
|
|
.freq_tab[1] = { \
|
|
.freq_clip_max = 200 * 1000, \
|
|
.temp_level = 103, \
|
|
}, \
|
|
.freq_tab_count = 2, \
|
|
.registers = &exynos5420_tmu_registers, \
|
|
|
|
#define EXYNOS5420_TMU_DATA \
|
|
__EXYNOS5420_TMU_DATA \
|
|
.type = SOC_ARCH_EXYNOS5250, \
|
|
.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
|
|
TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
|
|
TMU_SUPPORT_EMUL_TIME)
|
|
|
|
#define EXYNOS5420_TMU_DATA_SHARED \
|
|
__EXYNOS5420_TMU_DATA \
|
|
.type = SOC_ARCH_EXYNOS5420_TRIMINFO, \
|
|
.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
|
|
TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
|
|
TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
|
|
|
|
struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
|
|
.tmu_data = {
|
|
{ EXYNOS5420_TMU_DATA },
|
|
{ EXYNOS5420_TMU_DATA },
|
|
{ EXYNOS5420_TMU_DATA_SHARED },
|
|
{ EXYNOS5420_TMU_DATA_SHARED },
|
|
{ EXYNOS5420_TMU_DATA_SHARED },
|
|
},
|
|
.tmu_count = 5,
|
|
};
|
|
#endif
|
|
|
|
#if defined(CONFIG_SOC_EXYNOS5440)
|
|
static const struct exynos_tmu_registers exynos5440_tmu_registers = {
|
|
.triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
|
|
.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
|
|
.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
|
|
.tmu_ctrl = EXYNOS5440_TMU_S0_7_CTRL,
|
|
.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
|
|
.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
|
|
.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
|
|
.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
|
|
.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
|
|
.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
|
|
.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
|
|
.calib_mode_shift = EXYNOS_TMU_CALIB_MODE_SHIFT,
|
|
.calib_mode_mask = EXYNOS_TMU_CALIB_MODE_MASK,
|
|
.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
|
|
.tmu_status = EXYNOS5440_TMU_S0_7_STATUS,
|
|
.tmu_cur_temp = EXYNOS5440_TMU_S0_7_TEMP,
|
|
.threshold_th0 = EXYNOS5440_TMU_S0_7_TH0,
|
|
.threshold_th1 = EXYNOS5440_TMU_S0_7_TH1,
|
|
.threshold_th2 = EXYNOS5440_TMU_S0_7_TH2,
|
|
.threshold_th3_l0_shift = EXYNOS5440_TMU_TH_RISE4_SHIFT,
|
|
.tmu_inten = EXYNOS5440_TMU_S0_7_IRQEN,
|
|
.inten_rise0_shift = EXYNOS5440_TMU_INTEN_RISE0_SHIFT,
|
|
.inten_rise1_shift = EXYNOS5440_TMU_INTEN_RISE1_SHIFT,
|
|
.inten_rise2_shift = EXYNOS5440_TMU_INTEN_RISE2_SHIFT,
|
|
.inten_rise3_shift = EXYNOS5440_TMU_INTEN_RISE3_SHIFT,
|
|
.inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
|
|
.tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
|
|
.tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
|
|
.intclr_fall_shift = EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT,
|
|
.intclr_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
|
|
.intclr_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
|
|
.intclr_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
|
|
.tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
|
|
.emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
|
|
.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
|
|
.tmu_pmin = EXYNOS5440_TMU_PMIN,
|
|
};
|
|
|
|
#define EXYNOS5440_TMU_DATA \
|
|
.trigger_levels[0] = 100, \
|
|
.trigger_levels[4] = 105, \
|
|
.trigger_enable[0] = 1, \
|
|
.trigger_type[0] = SW_TRIP, \
|
|
.trigger_type[4] = HW_TRIP, \
|
|
.max_trigger_level = 5, \
|
|
.gain = 5, \
|
|
.reference_voltage = 16, \
|
|
.noise_cancel_mode = 4, \
|
|
.cal_type = TYPE_ONE_POINT_TRIMMING, \
|
|
.cal_mode = 0, \
|
|
.efuse_value = 0x5b2d, \
|
|
.min_efuse_value = 16, \
|
|
.max_efuse_value = 76, \
|
|
.first_point_trim = 25, \
|
|
.second_point_trim = 70, \
|
|
.default_temp_offset = 25, \
|
|
.type = SOC_ARCH_EXYNOS5440, \
|
|
.registers = &exynos5440_tmu_registers, \
|
|
.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
|
|
TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_ADDRESS_MULTIPLE),
|
|
|
|
struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
|
|
.tmu_data = {
|
|
{ EXYNOS5440_TMU_DATA } ,
|
|
{ EXYNOS5440_TMU_DATA } ,
|
|
{ EXYNOS5440_TMU_DATA } ,
|
|
},
|
|
.tmu_count = 3,
|
|
};
|
|
#endif
|