Huacai Chen f339bd3b51 Docs/LoongArch: Add advanced extended IRQ model description ... Introduce the advanced extended interrupt controllers (AVECINTC). This feature will allow each core to have 256 independent interrupt vectors and MSI interrupts can be independently routed to any vector on any CPU. The whole topology of irqchips in LoongArch machines looks like this if AVECINTC is supported: +-----+ +-----------------------+ +-------+ | IPI | --> | CPUINTC | <-- | Timer | +-----+ +-----------------------+ +-------+ ^ ^ ^ | | | +---------+ +----------+ +---------+ +-------+ | EIOINTC | | AVECINTC | | LIOINTC | <-- | UARTs | +---------+ +----------+ +---------+ +-------+ ^ ^ | | +---------+ +---------+ | PCH-PIC | | PCH-MSI | +---------+ +---------+ ^ ^ ^ | | | +---------+ +---------+ +---------+ | Devices | | PCH-LPC | | Devices | +---------+ +---------+ +---------+ ^ | +---------+ | Devices | +---------+ Signed-off-by: Huacai Chen <chenhuacai@loongson.cn> Signed-off-by: Tianyang Zhang <zhangtianyang@loongson.cn>		2024-09-24 15:32:20 +08:00
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it_IT	Docs: Move clang-format from process/ to dev-tools/	2024-06-26 16:36:00 -06:00
ja_JP	docs: ja_JP/howto: Catch up update in v6.8	2024-05-02 09:46:37 -06:00
ko_KR	Documentation/security-bugs: move from admin-guide/ to process/	2023-03-12 15:56:43 +01:00
sp_SP	docs/sp_SP: Add translation for scheduler/sched-design-CFS.rst	2024-07-09 09:14:33 -06:00
zh_CN	Docs/LoongArch: Add advanced extended IRQ model description	2024-09-24 15:32:20 +08:00
zh_TW	Nothing hugely exciting happening in the documentation tree this time	2024-07-18 15:54:16 -07:00
index.rst	Documentation: Start translations to Spanish	2022-11-01 16:58:29 -06:00