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95b00f6820
Clear FLR (Function Level Reset) from device capabilities registers for all physical functions. During FLR, the Margining Lane Status and Margining Lane Control registers should not be reset, as per PCIe specification. However, the controller incorrectly resets these registers upon FLR. This causes PCISIG compliance FLR test to fail. Hence preventing all functions from advertising FLR support if flag quirk_disable_flr is set. Link: https://lore.kernel.org/r/1635165075-89864-1-git-send-email-pthombar@cadence.com Signed-off-by: Parshuram Thombare <pthombar@cadence.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> |
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| .. | ||
| Kconfig | ||
| Makefile | ||
| pci-j721e.c | ||
| pcie-cadence-ep.c | ||
| pcie-cadence-host.c | ||
| pcie-cadence-plat.c | ||
| pcie-cadence.c | ||
| pcie-cadence.h | ||