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bcb63314e2
Drop the FSF's postal address from the source code files that typically
contain mostly the license text. Of the 628 removed instances, 578 are
outdated.
The patch has been created with the following command without manual edits:
git grep -l "675 Mass Ave\|59 Temple Place\|51 Franklin St" -- \
drivers/media/ include/media|while read i; do i=$i perl -e '
open(F,"< $ENV{i}");
$a=join("", <F>);
$a =~ s/[ \t]*\*\n.*You should.*\n.*along with.*\n.*(\n.*USA.*$)?\n//m
&& $a =~ s/(^.*)Or, (point your browser to) /$1To obtain the license, $2\n$1/m;
close(F);
open(F, "> $ENV{i}");
print F $a;
close(F);'; done
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
334 lines
8.3 KiB
C
334 lines
8.3 KiB
C
/*
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* mxl111sf-phy.c - driver for the MaxLinear MXL111SF
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*
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* Copyright (C) 2010-2014 Michael Krufky <mkrufky@linuxtv.org>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include "mxl111sf-phy.h"
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#include "mxl111sf-reg.h"
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int mxl111sf_init_tuner_demod(struct mxl111sf_state *state)
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{
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struct mxl111sf_reg_ctrl_info mxl_111_overwrite_default[] = {
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{0x07, 0xff, 0x0c},
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{0x58, 0xff, 0x9d},
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{0x09, 0xff, 0x00},
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{0x06, 0xff, 0x06},
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{0xc8, 0xff, 0x40}, /* ED_LE_WIN_OLD = 0 */
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{0x8d, 0x01, 0x01}, /* NEGATE_Q */
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{0x32, 0xff, 0xac}, /* DIG_RFREFSELECT = 12 */
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{0x42, 0xff, 0x43}, /* DIG_REG_AMP = 4 */
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{0x74, 0xff, 0xc4}, /* SSPUR_FS_PRIO = 4 */
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{0x71, 0xff, 0xe6}, /* SPUR_ROT_PRIO_VAL = 1 */
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{0x83, 0xff, 0x64}, /* INF_FILT1_THD_SC = 100 */
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{0x85, 0xff, 0x64}, /* INF_FILT2_THD_SC = 100 */
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{0x88, 0xff, 0xf0}, /* INF_THD = 240 */
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{0x6f, 0xf0, 0xb0}, /* DFE_DLY = 11 */
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{0x00, 0xff, 0x01}, /* Change to page 1 */
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{0x81, 0xff, 0x11}, /* DSM_FERR_BYPASS = 1 */
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{0xf4, 0xff, 0x07}, /* DIG_FREQ_CORR = 1 */
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{0xd4, 0x1f, 0x0f}, /* SPUR_TEST_NOISE_TH = 15 */
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{0xd6, 0xff, 0x0c}, /* SPUR_TEST_NOISE_PAPR = 12 */
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{0x00, 0xff, 0x00}, /* Change to page 0 */
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{0, 0, 0}
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};
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mxl_debug("()");
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return mxl111sf_ctrl_program_regs(state, mxl_111_overwrite_default);
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}
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int mxl1x1sf_soft_reset(struct mxl111sf_state *state)
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{
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int ret;
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mxl_debug("()");
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ret = mxl111sf_write_reg(state, 0xff, 0x00); /* AIC */
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if (mxl_fail(ret))
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goto fail;
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ret = mxl111sf_write_reg(state, 0x02, 0x01); /* get out of reset */
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mxl_fail(ret);
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fail:
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return ret;
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}
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int mxl1x1sf_set_device_mode(struct mxl111sf_state *state, int mode)
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{
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int ret;
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mxl_debug("(%s)", MXL_SOC_MODE == mode ?
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"MXL_SOC_MODE" : "MXL_TUNER_MODE");
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/* set device mode */
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ret = mxl111sf_write_reg(state, 0x03,
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MXL_SOC_MODE == mode ? 0x01 : 0x00);
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if (mxl_fail(ret))
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goto fail;
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ret = mxl111sf_write_reg_mask(state,
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0x7d, 0x40, MXL_SOC_MODE == mode ?
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0x00 : /* enable impulse noise filter,
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INF_BYP = 0 */
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0x40); /* disable impulse noise filter,
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INF_BYP = 1 */
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if (mxl_fail(ret))
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goto fail;
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state->device_mode = mode;
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fail:
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return ret;
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}
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/* power up tuner */
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int mxl1x1sf_top_master_ctrl(struct mxl111sf_state *state, int onoff)
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{
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mxl_debug("(%d)", onoff);
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return mxl111sf_write_reg(state, 0x01, onoff ? 0x01 : 0x00);
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}
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int mxl111sf_disable_656_port(struct mxl111sf_state *state)
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{
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mxl_debug("()");
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return mxl111sf_write_reg_mask(state, 0x12, 0x04, 0x00);
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}
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int mxl111sf_enable_usb_output(struct mxl111sf_state *state)
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{
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mxl_debug("()");
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return mxl111sf_write_reg_mask(state, 0x17, 0x40, 0x00);
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}
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/* initialize TSIF as input port of MxL1X1SF for MPEG2 data transfer */
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int mxl111sf_config_mpeg_in(struct mxl111sf_state *state,
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unsigned int parallel_serial,
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unsigned int msb_lsb_1st,
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unsigned int clock_phase,
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unsigned int mpeg_valid_pol,
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unsigned int mpeg_sync_pol)
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{
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int ret;
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u8 mode, tmp;
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mxl_debug("(%u,%u,%u,%u,%u)", parallel_serial, msb_lsb_1st,
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clock_phase, mpeg_valid_pol, mpeg_sync_pol);
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/* Enable PIN MUX */
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ret = mxl111sf_write_reg(state, V6_PIN_MUX_MODE_REG, V6_ENABLE_PIN_MUX);
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mxl_fail(ret);
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/* Configure MPEG Clock phase */
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mxl111sf_read_reg(state, V6_MPEG_IN_CLK_INV_REG, &mode);
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if (clock_phase == TSIF_NORMAL)
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mode &= ~V6_INVERTED_CLK_PHASE;
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else
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mode |= V6_INVERTED_CLK_PHASE;
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ret = mxl111sf_write_reg(state, V6_MPEG_IN_CLK_INV_REG, mode);
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mxl_fail(ret);
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/* Configure data input mode, MPEG Valid polarity, MPEG Sync polarity
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* Get current configuration */
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ret = mxl111sf_read_reg(state, V6_MPEG_IN_CTRL_REG, &mode);
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mxl_fail(ret);
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/* Data Input mode */
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if (parallel_serial == TSIF_INPUT_PARALLEL) {
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/* Disable serial mode */
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mode &= ~V6_MPEG_IN_DATA_SERIAL;
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/* Enable Parallel mode */
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mode |= V6_MPEG_IN_DATA_PARALLEL;
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} else {
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/* Disable Parallel mode */
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mode &= ~V6_MPEG_IN_DATA_PARALLEL;
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/* Enable Serial Mode */
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mode |= V6_MPEG_IN_DATA_SERIAL;
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/* If serial interface is chosen, configure
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MSB or LSB order in transmission */
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ret = mxl111sf_read_reg(state,
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V6_MPEG_INOUT_BIT_ORDER_CTRL_REG,
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&tmp);
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mxl_fail(ret);
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if (msb_lsb_1st == MPEG_SER_MSB_FIRST_ENABLED)
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tmp |= V6_MPEG_SER_MSB_FIRST;
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else
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tmp &= ~V6_MPEG_SER_MSB_FIRST;
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ret = mxl111sf_write_reg(state,
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V6_MPEG_INOUT_BIT_ORDER_CTRL_REG,
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tmp);
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mxl_fail(ret);
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}
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/* MPEG Sync polarity */
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if (mpeg_sync_pol == TSIF_NORMAL)
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mode &= ~V6_INVERTED_MPEG_SYNC;
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else
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mode |= V6_INVERTED_MPEG_SYNC;
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/* MPEG Valid polarity */
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if (mpeg_valid_pol == 0)
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mode &= ~V6_INVERTED_MPEG_VALID;
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else
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mode |= V6_INVERTED_MPEG_VALID;
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ret = mxl111sf_write_reg(state, V6_MPEG_IN_CTRL_REG, mode);
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mxl_fail(ret);
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return ret;
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}
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int mxl111sf_init_i2s_port(struct mxl111sf_state *state, u8 sample_size)
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{
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static struct mxl111sf_reg_ctrl_info init_i2s[] = {
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{0x1b, 0xff, 0x1e}, /* pin mux mode, Choose 656/I2S input */
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{0x15, 0x60, 0x60}, /* Enable I2S */
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{0x17, 0xe0, 0x20}, /* Input, MPEG MODE USB,
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Inverted 656 Clock, I2S_SOFT_RESET,
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0 : Normal operation, 1 : Reset State */
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#if 0
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{0x12, 0x01, 0x00}, /* AUDIO_IRQ_CLR (Overflow Indicator) */
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#endif
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{0x00, 0xff, 0x02}, /* Change to Control Page */
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{0x26, 0x0d, 0x0d}, /* I2S_MODE & BT656_SRC_SEL for FPGA only */
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{0x00, 0xff, 0x00},
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{0, 0, 0}
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};
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int ret;
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mxl_debug("(0x%02x)", sample_size);
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ret = mxl111sf_ctrl_program_regs(state, init_i2s);
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if (mxl_fail(ret))
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goto fail;
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ret = mxl111sf_write_reg(state, V6_I2S_NUM_SAMPLES_REG, sample_size);
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mxl_fail(ret);
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fail:
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return ret;
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}
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int mxl111sf_disable_i2s_port(struct mxl111sf_state *state)
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{
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static struct mxl111sf_reg_ctrl_info disable_i2s[] = {
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{0x15, 0x40, 0x00},
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{0, 0, 0}
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};
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mxl_debug("()");
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return mxl111sf_ctrl_program_regs(state, disable_i2s);
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}
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int mxl111sf_config_i2s(struct mxl111sf_state *state,
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u8 msb_start_pos, u8 data_width)
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{
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int ret;
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u8 tmp;
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mxl_debug("(0x%02x, 0x%02x)", msb_start_pos, data_width);
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ret = mxl111sf_read_reg(state, V6_I2S_STREAM_START_BIT_REG, &tmp);
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if (mxl_fail(ret))
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goto fail;
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tmp &= 0xe0;
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tmp |= msb_start_pos;
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ret = mxl111sf_write_reg(state, V6_I2S_STREAM_START_BIT_REG, tmp);
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if (mxl_fail(ret))
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goto fail;
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ret = mxl111sf_read_reg(state, V6_I2S_STREAM_END_BIT_REG, &tmp);
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if (mxl_fail(ret))
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goto fail;
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tmp &= 0xe0;
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tmp |= data_width;
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ret = mxl111sf_write_reg(state, V6_I2S_STREAM_END_BIT_REG, tmp);
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mxl_fail(ret);
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fail:
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return ret;
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}
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int mxl111sf_config_spi(struct mxl111sf_state *state, int onoff)
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{
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u8 val;
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int ret;
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mxl_debug("(%d)", onoff);
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ret = mxl111sf_write_reg(state, 0x00, 0x02);
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if (mxl_fail(ret))
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goto fail;
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ret = mxl111sf_read_reg(state, V8_SPI_MODE_REG, &val);
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if (mxl_fail(ret))
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goto fail;
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if (onoff)
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val |= 0x04;
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else
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val &= ~0x04;
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ret = mxl111sf_write_reg(state, V8_SPI_MODE_REG, val);
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if (mxl_fail(ret))
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goto fail;
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ret = mxl111sf_write_reg(state, 0x00, 0x00);
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mxl_fail(ret);
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fail:
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return ret;
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}
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int mxl111sf_idac_config(struct mxl111sf_state *state,
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u8 control_mode, u8 current_setting,
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u8 current_value, u8 hysteresis_value)
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{
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int ret;
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u8 val;
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/* current value will be set for both automatic & manual IDAC control */
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val = current_value;
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if (control_mode == IDAC_MANUAL_CONTROL) {
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/* enable manual control of IDAC */
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val |= IDAC_MANUAL_CONTROL_BIT_MASK;
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if (current_setting == IDAC_CURRENT_SINKING_ENABLE)
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/* enable current sinking in manual mode */
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val |= IDAC_CURRENT_SINKING_BIT_MASK;
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else
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/* disable current sinking in manual mode */
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val &= ~IDAC_CURRENT_SINKING_BIT_MASK;
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} else {
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/* disable manual control of IDAC */
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val &= ~IDAC_MANUAL_CONTROL_BIT_MASK;
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/* set hysteresis value reg: 0x0B<5:0> */
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ret = mxl111sf_write_reg(state, V6_IDAC_HYSTERESIS_REG,
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(hysteresis_value & 0x3F));
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mxl_fail(ret);
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}
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ret = mxl111sf_write_reg(state, V6_IDAC_SETTINGS_REG, val);
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mxl_fail(ret);
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return ret;
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}
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