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The CPSW ALE supports feature to rate limit number ingress broadcast(BC)/multicast(MC) packets per/sec which main purpose is BC/MC storm prevention. The ALE BC/MC packet rate limit configuration consist of two parts: - global ALE_CONTROL.ENABLE_RATE_LIMIT bit 0 which enables rate limiting globally ALE_PRESCALE.PRESCALE specifies rate limiting interval - per-port ALE_PORTCTLx.BCASTMCAST/_LIMIT specifies number of BC/MC packets allowed per rate limiting interval. When port.BCASTMCAST/_LIMIT is 0 rate limiting is disabled for Port. When BC/MC packet rate limiting is enabled the number of allowed packets per/sec is defined as: number_of_packets/sec = (Fclk / ALE_PRESCALE) * port.BCASTMCAST/_LIMIT Hence, the ALE_PRESCALE configuration is common for all ports the 1ms interval is selected and configured during ALE initialization while port.BCAST/MCAST_LIMIT are configured per-port. This allows to achieve: - min number_of_packets = 1000 when port.BCAST/MCAST_LIMIT = 1 - max number_of_packets = 1000 * 255 = 255000 when port.BCAST/MCAST_LIMIT = 0xFF The ALE_CONTROL.ENABLE_RATE_LIMIT can also be enabled once during ALE initialization as rate limiting enabled by non zero port.BCASTMCAST/_LIMIT values. This patch implements above logic in ALE and adds new ALE APIs cpsw_ale_rx_ratelimit_bc(); cpsw_ale_rx_ratelimit_mc(); Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: David S. Miller <davem@davemloft.net>
144 lines
4.2 KiB
C
144 lines
4.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Texas Instruments N-Port Ethernet Switch Address Lookup Engine APIs
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*
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* Copyright (C) 2012 Texas Instruments
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*
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*/
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#ifndef __TI_CPSW_ALE_H__
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#define __TI_CPSW_ALE_H__
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struct cpsw_ale_params {
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struct device *dev;
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void __iomem *ale_regs;
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unsigned long ale_ageout; /* in secs */
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unsigned long ale_entries;
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unsigned long ale_ports;
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/* NU Switch has specific handling as number of bits in ALE entries
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* are different than other versions of ALE. Also there are specific
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* registers for unknown vlan specific fields. So use nu_switch_ale
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* to identify this hardware.
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*/
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bool nu_switch_ale;
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/* mask bit used in NU Switch ALE is 3 bits instead of 8 bits. So
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* pass it from caller.
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*/
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u32 major_ver_mask;
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const char *dev_id;
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unsigned long bus_freq;
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};
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struct ale_entry_fld;
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struct cpsw_ale {
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struct cpsw_ale_params params;
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struct timer_list timer;
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unsigned long ageout;
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u32 version;
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u32 features;
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/* These bits are different on NetCP NU Switch ALE */
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u32 port_mask_bits;
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u32 port_num_bits;
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u32 vlan_field_bits;
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unsigned long *p0_untag_vid_mask;
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const struct ale_entry_fld *vlan_entry_tbl;
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};
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enum cpsw_ale_control {
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/* global */
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ALE_ENABLE,
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ALE_CLEAR,
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ALE_AGEOUT,
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ALE_P0_UNI_FLOOD,
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ALE_VLAN_NOLEARN,
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ALE_NO_PORT_VLAN,
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ALE_OUI_DENY,
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ALE_BYPASS,
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ALE_RATE_LIMIT_TX,
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ALE_VLAN_AWARE,
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ALE_AUTH_ENABLE,
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ALE_RATE_LIMIT,
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/* port controls */
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ALE_PORT_STATE,
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ALE_PORT_DROP_UNTAGGED,
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ALE_PORT_DROP_UNKNOWN_VLAN,
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ALE_PORT_NOLEARN,
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ALE_PORT_NO_SA_UPDATE,
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ALE_PORT_UNKNOWN_VLAN_MEMBER,
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ALE_PORT_UNKNOWN_MCAST_FLOOD,
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ALE_PORT_UNKNOWN_REG_MCAST_FLOOD,
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ALE_PORT_UNTAGGED_EGRESS,
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ALE_PORT_MACONLY,
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ALE_PORT_MACONLY_CAF,
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ALE_PORT_BCAST_LIMIT,
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ALE_PORT_MCAST_LIMIT,
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ALE_DEFAULT_THREAD_ID,
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ALE_DEFAULT_THREAD_ENABLE,
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ALE_NUM_CONTROLS,
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};
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enum cpsw_ale_port_state {
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ALE_PORT_STATE_DISABLE = 0x00,
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ALE_PORT_STATE_BLOCK = 0x01,
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ALE_PORT_STATE_LEARN = 0x02,
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ALE_PORT_STATE_FORWARD = 0x03,
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};
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/* ALE unicast entry flags - passed into cpsw_ale_add_ucast() */
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#define ALE_SECURE BIT(0)
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#define ALE_BLOCKED BIT(1)
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#define ALE_SUPER BIT(2)
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#define ALE_VLAN BIT(3)
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#define ALE_PORT_HOST BIT(0)
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#define ALE_PORT_1 BIT(1)
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#define ALE_PORT_2 BIT(2)
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#define ALE_MCAST_FWD 0
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#define ALE_MCAST_BLOCK_LEARN_FWD 1
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#define ALE_MCAST_FWD_LEARN 2
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#define ALE_MCAST_FWD_2 3
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#define ALE_ENTRY_BITS 68
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#define ALE_ENTRY_WORDS DIV_ROUND_UP(ALE_ENTRY_BITS, 32)
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struct cpsw_ale *cpsw_ale_create(struct cpsw_ale_params *params);
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void cpsw_ale_start(struct cpsw_ale *ale);
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void cpsw_ale_stop(struct cpsw_ale *ale);
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int cpsw_ale_flush_multicast(struct cpsw_ale *ale, int port_mask, int vid);
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int cpsw_ale_add_ucast(struct cpsw_ale *ale, const u8 *addr, int port,
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int flags, u16 vid);
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int cpsw_ale_del_ucast(struct cpsw_ale *ale, const u8 *addr, int port,
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int flags, u16 vid);
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int cpsw_ale_add_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask,
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int flags, u16 vid, int mcast_state);
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int cpsw_ale_del_mcast(struct cpsw_ale *ale, const u8 *addr, int port_mask,
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int flags, u16 vid);
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int cpsw_ale_add_vlan(struct cpsw_ale *ale, u16 vid, int port, int untag,
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int reg_mcast, int unreg_mcast);
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int cpsw_ale_del_vlan(struct cpsw_ale *ale, u16 vid, int port);
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void cpsw_ale_set_allmulti(struct cpsw_ale *ale, int allmulti, int port);
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int cpsw_ale_rx_ratelimit_bc(struct cpsw_ale *ale, int port, unsigned int ratelimit_pps);
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int cpsw_ale_rx_ratelimit_mc(struct cpsw_ale *ale, int port, unsigned int ratelimit_pps);
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int cpsw_ale_control_get(struct cpsw_ale *ale, int port, int control);
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int cpsw_ale_control_set(struct cpsw_ale *ale, int port,
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int control, int value);
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void cpsw_ale_dump(struct cpsw_ale *ale, u32 *data);
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u32 cpsw_ale_get_num_entries(struct cpsw_ale *ale);
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static inline int cpsw_ale_get_vlan_p0_untag(struct cpsw_ale *ale, u16 vid)
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{
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return test_bit(vid, ale->p0_untag_vid_mask);
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}
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int cpsw_ale_vlan_add_modify(struct cpsw_ale *ale, u16 vid, int port_mask,
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int untag_mask, int reg_mcast, int unreg_mcast);
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int cpsw_ale_vlan_del_modify(struct cpsw_ale *ale, u16 vid, int port_mask);
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void cpsw_ale_set_unreg_mcast(struct cpsw_ale *ale, int unreg_mcast_mask,
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bool add);
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#endif
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