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278a6752e8
add core.c, clock.c, and clock.h in mach-bcmring implement timer init, clocksource init, amba device init implement clock set/get enable/disable API add dummy clkdev.h Signed-off-by: Leo Chen <leochen@broadcom.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
225 lines
5.0 KiB
C
225 lines
5.0 KiB
C
/*****************************************************************************
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* Copyright 2001 - 2009 Broadcom Corporation. All rights reserved.
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*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to you
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* under the terms of the GNU General Public License version 2, available at
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* http://www.broadcom.com/licenses/GPLv2.php (the "GPL").
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*
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* Notwithstanding the above, under no circumstances may you combine this
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* software in any way with any other Broadcom software provided under a
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* license other than the GPL, without Broadcom's express prior written
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* consent.
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*****************************************************************************/
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/device.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/string.h>
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#include <linux/clk.h>
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#include <linux/spinlock.h>
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#include <mach/csp/hw_cfg.h>
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#include <mach/csp/chipcHw_def.h>
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#include <mach/csp/chipcHw_reg.h>
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#include <mach/csp/chipcHw_inline.h>
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#include <asm/clkdev.h>
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#include "clock.h"
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#define clk_is_primary(x) ((x)->type & CLK_TYPE_PRIMARY)
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#define clk_is_pll1(x) ((x)->type & CLK_TYPE_PLL1)
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#define clk_is_pll2(x) ((x)->type & CLK_TYPE_PLL2)
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#define clk_is_programmable(x) ((x)->type & CLK_TYPE_PROGRAMMABLE)
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#define clk_is_bypassable(x) ((x)->type & CLK_TYPE_BYPASSABLE)
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#define clk_is_using_xtal(x) ((x)->mode & CLK_MODE_XTAL)
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static DEFINE_SPINLOCK(clk_lock);
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static void __clk_enable(struct clk *clk)
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{
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if (!clk)
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return;
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/* enable parent clock first */
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if (clk->parent)
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__clk_enable(clk->parent);
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if (clk->use_cnt++ == 0) {
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if (clk_is_pll1(clk)) { /* PLL1 */
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chipcHw_pll1Enable(clk->rate_hz, 0);
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} else if (clk_is_pll2(clk)) { /* PLL2 */
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chipcHw_pll2Enable(clk->rate_hz);
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} else if (clk_is_using_xtal(clk)) { /* source is crystal */
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if (!clk_is_primary(clk))
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chipcHw_bypassClockEnable(clk->csp_id);
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} else { /* source is PLL */
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chipcHw_setClockEnable(clk->csp_id);
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}
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}
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}
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int clk_enable(struct clk *clk)
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{
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unsigned long flags;
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if (!clk)
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return -EINVAL;
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spin_lock_irqsave(&clk_lock, flags);
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__clk_enable(clk);
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spin_unlock_irqrestore(&clk_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(clk_enable);
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static void __clk_disable(struct clk *clk)
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{
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if (!clk)
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return;
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BUG_ON(clk->use_cnt == 0);
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if (--clk->use_cnt == 0) {
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if (clk_is_pll1(clk)) { /* PLL1 */
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chipcHw_pll1Disable();
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} else if (clk_is_pll2(clk)) { /* PLL2 */
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chipcHw_pll2Disable();
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} else if (clk_is_using_xtal(clk)) { /* source is crystal */
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if (!clk_is_primary(clk))
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chipcHw_bypassClockDisable(clk->csp_id);
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} else { /* source is PLL */
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chipcHw_setClockDisable(clk->csp_id);
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}
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}
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if (clk->parent)
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__clk_disable(clk->parent);
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}
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void clk_disable(struct clk *clk)
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{
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unsigned long flags;
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if (!clk)
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return;
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spin_lock_irqsave(&clk_lock, flags);
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__clk_disable(clk);
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spin_unlock_irqrestore(&clk_lock, flags);
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}
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EXPORT_SYMBOL(clk_disable);
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unsigned long clk_get_rate(struct clk *clk)
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{
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if (!clk)
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return 0;
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return clk->rate_hz;
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}
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EXPORT_SYMBOL(clk_get_rate);
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long clk_round_rate(struct clk *clk, unsigned long rate)
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{
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unsigned long flags;
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unsigned long actual;
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unsigned long rate_hz;
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if (!clk)
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return -EINVAL;
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if (!clk_is_programmable(clk))
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return -EINVAL;
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if (clk->use_cnt)
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return -EBUSY;
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spin_lock_irqsave(&clk_lock, flags);
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actual = clk->parent->rate_hz;
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rate_hz = min(actual, rate);
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spin_unlock_irqrestore(&clk_lock, flags);
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return rate_hz;
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}
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EXPORT_SYMBOL(clk_round_rate);
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int clk_set_rate(struct clk *clk, unsigned long rate)
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{
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unsigned long flags;
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unsigned long actual;
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unsigned long rate_hz;
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if (!clk)
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return -EINVAL;
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if (!clk_is_programmable(clk))
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return -EINVAL;
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if (clk->use_cnt)
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return -EBUSY;
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spin_lock_irqsave(&clk_lock, flags);
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actual = clk->parent->rate_hz;
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rate_hz = min(actual, rate);
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rate_hz = chipcHw_setClockFrequency(clk->csp_id, rate_hz);
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clk->rate_hz = rate_hz;
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spin_unlock_irqrestore(&clk_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(clk_set_rate);
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struct clk *clk_get_parent(struct clk *clk)
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{
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if (!clk)
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return NULL;
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return clk->parent;
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}
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EXPORT_SYMBOL(clk_get_parent);
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int clk_set_parent(struct clk *clk, struct clk *parent)
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{
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unsigned long flags;
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struct clk *old_parent;
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if (!clk || !parent)
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return -EINVAL;
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if (!clk_is_primary(parent) || !clk_is_bypassable(clk))
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return -EINVAL;
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/* if more than one user, parent is not allowed */
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if (clk->use_cnt > 1)
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return -EBUSY;
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if (clk->parent == parent)
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return 0;
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spin_lock_irqsave(&clk_lock, flags);
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old_parent = clk->parent;
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clk->parent = parent;
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if (clk_is_using_xtal(parent))
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clk->mode |= CLK_MODE_XTAL;
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else
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clk->mode &= (~CLK_MODE_XTAL);
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/* if clock is active */
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if (clk->use_cnt != 0) {
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clk->use_cnt--;
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/* enable clock with the new parent */
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__clk_enable(clk);
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/* disable the old parent */
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__clk_disable(old_parent);
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}
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spin_unlock_irqrestore(&clk_lock, flags);
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return 0;
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}
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EXPORT_SYMBOL(clk_set_parent);
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