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SiRFprimaII is the latest generation application processor from CSR’s multi-function SoC product family. The SoC support codes are in arch/arm/mach-prima2 from Linux mainline 3.0. There are two I2C controllers on primaII, features include: * Two I2C controller modules are on chip * RISC I/O bus read write register * Up to 16 bytes data buffer for issuing commands and writing data at the same time * Up to 16 commands, and receiving read data 16 bytes at a time * Error INT report (ACK check) * No-ACK bus protocols (SCCB bus protocols) Signed-off-by: Zhiwu Song <Zhiwu.Song@csr.com> Signed-off-by: Xiangzhen Ye <Xiangzhen.Ye@csr.com> Signed-off-by: Yuping Luo <Yuping.Luo@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
20 lines
523 B
Plaintext
20 lines
523 B
Plaintext
I2C for SiRFprimaII platforms
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Required properties :
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- compatible : Must be "sirf,prima2-i2c"
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- reg: physical base address of the controller and length of memory mapped
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region.
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- interrupts: interrupt number to the cpu.
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Optional properties:
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- clock-frequency : Constains desired I2C/HS-I2C bus clock frequency in Hz.
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The absence of the propoerty indicates the default frequency 100 kHz.
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Examples :
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i2c0: i2c@b00e0000 {
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compatible = "sirf,prima2-i2c";
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reg = <0xb00e0000 0x10000>;
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interrupts = <24>;
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};
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