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ef833eab1d
With corresponding clk driver now merged upstream, switch to it. - core_clk now represent the PLL (vs. fixed clk before) - input_clk represent the clk signal src for PLL (basically xtal) Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com> |
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oprofile | ||
plat-axs10x | ||
plat-eznps | ||
plat-hsdk | ||
plat-sim | ||
plat-tb10x | ||
Kbuild | ||
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Kconfig.debug | ||
Makefile |