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ef6eb322ce
The Nomadik clock implementation was a stub just using
fixed clocks.
This implements the clocks properly instead of relying
on them all being on at boot and leaving them all on.
The PLLs are on the top locking to the main chrystal
oscillator, then the HCLK for the peripherals are
below PLL2.
The gated clocks are implemented with zero cells and
given the clock ID as a property of each node, so every
gate need to have its own node in the device tree.
This is because the gate registers contain both HCLK
gates and PCLK gates, where the latter has HCLK as
parent. As can be seen from the register layout, this
is a complete mixup, which means all these gates need
their own node to properly model parent/child relations
for PCLKs apart from the HCLKs.
This driver also adds a helpful debugfs file to inspect
the hardware state of the clock gates.
This is the end result in <debugfs>/clk/clk_summary
after applying a proper device tree:
ulpiclk 0 0 60000000
mxtal 3 3 19200000
pll2 1 1 864000000
clk48 3 3 48000000
rngcclk 1 1 48000000
usbmclk 0 0 48000000
mshcclk 0 0 48000000
mspclk3 0 0 48000000
x3dclk 0 0 48000000
skeclk 0 0 48000000
owmclk 0 0 48000000
mspclk2 0 0 48000000
mspclk1 0 0 48000000
uart2clk 0 0 48000000
ipbmcclk 0 0 48000000
ipi2cclk 0 0 48000000
usbclk 0 0 48000000
mspclk0 0 0 48000000
uart1clk 1 2 48000000
i2c1clk 0 0 48000000
i2c0clk 0 0 48000000
sdiclk 1 1 48000000
uart0clk 0 0 48000000
sspiclk 0 0 48000000
irdaclk 0 0 48000000
clk72 0 0 72000000
difclk 0 0 72000000
clcdclk 0 0 72000000
clk216 0 0 216000000
hsiclkrx 0 0 216000000
clk108 0 0 108000000
hsiclktx 0 0 108000000
clk27 0 0 27000000
pll1 1 1 264000000
hclk 3 3 264000000
hclkrng 1 1 264000000
hclkusbm 0 0 264000000
hclkcryp 0 0 264000000
hclkhash 0 0 264000000
hclk3d 0 0 264000000
hclkhpi 0 0 264000000
hclksva 0 0 264000000
hclksaa 0 0 264000000
hclkdif 0 0 264000000
hclkusb 0 0 264000000
hclkclcd 0 0 264000000
hclkdma1 0 0 264000000
hclksdram 0 0 264000000
hclksmc 1 1 264000000
hclkdma0 0 0 264000000
pclk 7 9 264000000
pclkmsp3 0 0 264000000
pclkmshc 0 0 264000000
pclkhsem 0 0 264000000
pclkske 0 0 264000000
pclkowm 0 0 264000000
pclkmsp2 0 0 264000000
pclkmsp1 0 0 264000000
pclkuart2 0 0 264000000
pclkxti 0 0 264000000
pclkhsi 0 0 264000000
pclkmsp0 0 0 264000000
pclkuart1 1 1 264000000
pclki2c1 0 0 264000000
pclki2c0 0 0 264000000
pclksdi 1 1 264000000
pclkuart0 1 1 264000000
pclkssp 0 0 264000000
pclkirda 0 0 264000000
timclk 1 1 2400000
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
105 lines
2.3 KiB
Plaintext
105 lines
2.3 KiB
Plaintext
ST Microelectronics Nomadik SRC System Reset and Control
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This binding uses the common clock binding:
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Documentation/devicetree/bindings/clock/clock-bindings.txt
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The Nomadik SRC controller is responsible of controlling chrystals,
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PLLs and clock gates.
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Required properties for the SRC node:
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- compatible: must be "stericsson,nomadik-src"
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- reg: must contain the SRC register base and size
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Optional properties for the SRC node:
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- disable-sxtalo: if present this will disable the SXTALO
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i.e. the driver output for the slow 32kHz chrystal, if the
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board has its own circuitry for providing this oscillator
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- disable-mxtal: if present this will disable the MXTALO,
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i.e. the driver output for the main (~19.2 MHz) chrystal,
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if the board has its own circuitry for providing this
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osciallator
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PLL nodes: these nodes represent the two PLLs on the system,
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which should both have the main chrystal, represented as a
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fixed frequency clock, as parent.
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Required properties for the two PLL nodes:
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- compatible: must be "st,nomadik-pll-clock"
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- clock-cells: must be 0
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- clock-id: must be 1 or 2 for PLL1 and PLL2 respectively
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- clocks: this clock will have main chrystal as parent
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HCLK nodes: these represent the clock gates on individual
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lines from the HCLK clock tree and the gate for individual
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lines from the PCLK clock tree.
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Requires properties for the HCLK nodes:
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- compatible: must be "st,nomadik-hclk-clock"
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- clock-cells: must be 0
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- clock-id: must be the clock ID from 0 to 63 according to
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this table:
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0: HCLKDMA0
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1: HCLKSMC
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2: HCLKSDRAM
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3: HCLKDMA1
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4: HCLKCLCD
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5: PCLKIRDA
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6: PCLKSSP
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7: PCLKUART0
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8: PCLKSDI
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9: PCLKI2C0
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10: PCLKI2C1
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11: PCLKUART1
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12: PCLMSP0
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13: HCLKUSB
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14: HCLKDIF
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15: HCLKSAA
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16: HCLKSVA
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17: PCLKHSI
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18: PCLKXTI
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19: PCLKUART2
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20: PCLKMSP1
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21: PCLKMSP2
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22: PCLKOWM
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23: HCLKHPI
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24: PCLKSKE
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25: PCLKHSEM
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26: HCLK3D
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27: HCLKHASH
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28: HCLKCRYP
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29: PCLKMSHC
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30: HCLKUSBM
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31: HCLKRNG
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(32, 33, 34, 35 RESERVED)
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36: CLDCLK
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37: IRDACLK
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38: SSPICLK
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39: UART0CLK
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40: SDICLK
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41: I2C0CLK
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42: I2C1CLK
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43: UART1CLK
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44: MSPCLK0
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45: USBCLK
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46: DIFCLK
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47: IPI2CCLK
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48: IPBMCCLK
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49: HSICLKRX
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50: HSICLKTX
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51: UART2CLK
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52: MSPCLK1
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53: MSPCLK2
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54: OWMCLK
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(55 RESERVED)
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56: SKECLK
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(57 RESERVED)
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58: 3DCLK
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59: PCLKMSP3
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60: MSPCLK3
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61: MSHCCLK
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62: USBMCLK
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63: RNGCCLK
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