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5e037e7480
Add support for two MAC addresses. If the NVS has a valid MAC address, that takes precedence and we use two sequential address starting from the one specified. If the NVS doesn't contain a valid MAC address (ie. if it is set to 00:00:00:00:00:00), we check if the HW PG version in use has the BD_ADDR written in the fuse ROM. If it does, we read it and derive the two subsequent addresses for WLAN. During production, 3 addresses are reserved per device. The first for Bluetooth (burnt in the fuse ROM) and the following two for WLAN. This patch has some code by Igal and Arik (squashed from internal patches). Signed-off-by: Arik Nemtsov <arik@wizery.com> Signed-off-by: Igal Chernobelsky <igalc@ti.com> Signed-off-by: Luciano Coelho <coelho@ti.com>
556 lines
20 KiB
C
556 lines
20 KiB
C
/*
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* This file is part of wl12xx
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*
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* Copyright (C) 1998-2009 Texas Instruments. All rights reserved.
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* Copyright (C) 2009 Nokia Corporation
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*
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* Contact: Luciano Coelho <luciano.coelho@nokia.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#ifndef __REG_H__
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#define __REG_H__
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#include <linux/bitops.h>
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#define REGISTERS_BASE 0x00300000
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#define DRPW_BASE 0x00310000
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#define REGISTERS_DOWN_SIZE 0x00008800
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#define REGISTERS_WORK_SIZE 0x0000b000
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#define HW_ACCESS_ELP_CTRL_REG_ADDR 0x1FFFC
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#define FW_STATUS_ADDR (0x14FC0 + 0xA000)
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/* ELP register commands */
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#define ELPCTRL_WAKE_UP 0x1
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#define ELPCTRL_WAKE_UP_WLAN_READY 0x5
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#define ELPCTRL_SLEEP 0x0
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/* ELP WLAN_READY bit */
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#define ELPCTRL_WLAN_READY 0x2
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/*===============================================
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Host Software Reset - 32bit RW
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------------------------------------------
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[31:1] Reserved
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0 SOFT_RESET Soft Reset - When this bit is set,
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it holds the Wlan hardware in a soft reset state.
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This reset disables all MAC and baseband processor
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clocks except the CardBus/PCI interface clock.
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It also initializes all MAC state machines except
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the host interface. It does not reload the
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contents of the EEPROM. When this bit is cleared
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(not self-clearing), the Wlan hardware
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exits the software reset state.
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===============================================*/
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#define ACX_REG_SLV_SOFT_RESET (REGISTERS_BASE + 0x0000)
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#define WL1271_SLV_REG_DATA (REGISTERS_BASE + 0x0008)
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#define WL1271_SLV_REG_ADATA (REGISTERS_BASE + 0x000c)
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#define WL1271_SLV_MEM_DATA (REGISTERS_BASE + 0x0018)
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#define ACX_REG_INTERRUPT_TRIG (REGISTERS_BASE + 0x0474)
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#define ACX_REG_INTERRUPT_TRIG_H (REGISTERS_BASE + 0x0478)
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/*=============================================
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Host Interrupt Mask Register - 32bit (RW)
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------------------------------------------
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Setting a bit in this register masks the
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corresponding interrupt to the host.
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0 - RX0 - Rx first dubble buffer Data Interrupt
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1 - TXD - Tx Data Interrupt
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2 - TXXFR - Tx Transfer Interrupt
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3 - RX1 - Rx second dubble buffer Data Interrupt
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4 - RXXFR - Rx Transfer Interrupt
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5 - EVENT_A - Event Mailbox interrupt
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6 - EVENT_B - Event Mailbox interrupt
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7 - WNONHST - Wake On Host Interrupt
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8 - TRACE_A - Debug Trace interrupt
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9 - TRACE_B - Debug Trace interrupt
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10 - CDCMP - Command Complete Interrupt
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11 -
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12 -
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13 -
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14 - ICOMP - Initialization Complete Interrupt
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16 - SG SE - Soft Gemini - Sense enable interrupt
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17 - SG SD - Soft Gemini - Sense disable interrupt
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18 - -
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19 - -
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20 - -
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21- -
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Default: 0x0001
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*==============================================*/
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#define ACX_REG_INTERRUPT_MASK (REGISTERS_BASE + 0x04DC)
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/*=============================================
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Host Interrupt Mask Set 16bit, (Write only)
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------------------------------------------
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Setting a bit in this register sets
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the corresponding bin in ACX_HINT_MASK register
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without effecting the mask
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state of other bits (0 = no effect).
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==============================================*/
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#define ACX_REG_HINT_MASK_SET (REGISTERS_BASE + 0x04E0)
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/*=============================================
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Host Interrupt Mask Clear 16bit,(Write only)
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------------------------------------------
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Setting a bit in this register clears
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the corresponding bin in ACX_HINT_MASK register
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without effecting the mask
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state of other bits (0 = no effect).
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=============================================*/
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#define ACX_REG_HINT_MASK_CLR (REGISTERS_BASE + 0x04E4)
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/*=============================================
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Host Interrupt Status Nondestructive Read
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16bit,(Read only)
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------------------------------------------
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The host can read this register to determine
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which interrupts are active.
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Reading this register doesn't
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effect its content.
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=============================================*/
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#define ACX_REG_INTERRUPT_NO_CLEAR (REGISTERS_BASE + 0x04E8)
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/*=============================================
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Host Interrupt Status Clear on Read Register
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16bit,(Read only)
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------------------------------------------
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The host can read this register to determine
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which interrupts are active.
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Reading this register clears it,
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thus making all interrupts inactive.
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==============================================*/
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#define ACX_REG_INTERRUPT_CLEAR (REGISTERS_BASE + 0x04F8)
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/*=============================================
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Host Interrupt Acknowledge Register
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16bit,(Write only)
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------------------------------------------
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The host can set individual bits in this
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register to clear (acknowledge) the corresp.
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interrupt status bits in the HINT_STS_CLR and
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HINT_STS_ND registers, thus making the
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assotiated interrupt inactive. (0-no effect)
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==============================================*/
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#define ACX_REG_INTERRUPT_ACK (REGISTERS_BASE + 0x04F0)
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#define RX_DRIVER_COUNTER_ADDRESS (REGISTERS_BASE + 0x0538)
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/* Device Configuration registers*/
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#define SOR_CFG (REGISTERS_BASE + 0x0800)
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/* Embedded ARM CPU Control */
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/*===============================================
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Halt eCPU - 32bit RW
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------------------------------------------
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0 HALT_ECPU Halt Embedded CPU - This bit is the
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compliment of bit 1 (MDATA2) in the SOR_CFG register.
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During a hardware reset, this bit holds
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the inverse of MDATA2.
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When downloading firmware from the host,
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set this bit (pull down MDATA2).
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The host clears this bit after downloading the firmware into
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zero-wait-state SSRAM.
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When loading firmware from Flash, clear this bit (pull up MDATA2)
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so that the eCPU can run the bootloader code in Flash
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HALT_ECPU eCPU State
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--------------------
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1 halt eCPU
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0 enable eCPU
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===============================================*/
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#define ACX_REG_ECPU_CONTROL (REGISTERS_BASE + 0x0804)
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#define HI_CFG (REGISTERS_BASE + 0x0808)
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/*===============================================
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EEPROM Burst Read Start - 32bit RW
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------------------------------------------
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[31:1] Reserved
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0 ACX_EE_START - EEPROM Burst Read Start 0
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Setting this bit starts a burst read from
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the external EEPROM.
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If this bit is set (after reset) before an EEPROM read/write,
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the burst read starts at EEPROM address 0.
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Otherwise, it starts at the address
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following the address of the previous access.
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TheWlan hardware hardware clears this bit automatically.
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Default: 0x00000000
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*================================================*/
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#define ACX_REG_EE_START (REGISTERS_BASE + 0x080C)
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#define OCP_POR_CTR (REGISTERS_BASE + 0x09B4)
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#define OCP_DATA_WRITE (REGISTERS_BASE + 0x09B8)
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#define OCP_DATA_READ (REGISTERS_BASE + 0x09BC)
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#define OCP_CMD (REGISTERS_BASE + 0x09C0)
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#define WL1271_HOST_WR_ACCESS (REGISTERS_BASE + 0x09F8)
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#define CHIP_ID_B (REGISTERS_BASE + 0x5674)
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#define CHIP_ID_1271_PG10 (0x4030101)
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#define CHIP_ID_1271_PG20 (0x4030111)
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#define CHIP_ID_1283_PG10 (0x05030101)
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#define CHIP_ID_1283_PG20 (0x05030111)
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#define ENABLE (REGISTERS_BASE + 0x5450)
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/* Power Management registers */
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#define ELP_CFG_MODE (REGISTERS_BASE + 0x5804)
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#define ELP_CMD (REGISTERS_BASE + 0x5808)
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#define PLL_CAL_TIME (REGISTERS_BASE + 0x5810)
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#define CLK_REQ_TIME (REGISTERS_BASE + 0x5814)
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#define CLK_BUF_TIME (REGISTERS_BASE + 0x5818)
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#define CFG_PLL_SYNC_CNT (REGISTERS_BASE + 0x5820)
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/* Scratch Pad registers*/
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#define SCR_PAD0 (REGISTERS_BASE + 0x5608)
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#define SCR_PAD1 (REGISTERS_BASE + 0x560C)
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#define SCR_PAD2 (REGISTERS_BASE + 0x5610)
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#define SCR_PAD3 (REGISTERS_BASE + 0x5614)
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#define SCR_PAD4 (REGISTERS_BASE + 0x5618)
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#define SCR_PAD4_SET (REGISTERS_BASE + 0x561C)
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#define SCR_PAD4_CLR (REGISTERS_BASE + 0x5620)
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#define SCR_PAD5 (REGISTERS_BASE + 0x5624)
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#define SCR_PAD5_SET (REGISTERS_BASE + 0x5628)
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#define SCR_PAD5_CLR (REGISTERS_BASE + 0x562C)
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#define SCR_PAD6 (REGISTERS_BASE + 0x5630)
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#define SCR_PAD7 (REGISTERS_BASE + 0x5634)
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#define SCR_PAD8 (REGISTERS_BASE + 0x5638)
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#define SCR_PAD9 (REGISTERS_BASE + 0x563C)
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/* Spare registers*/
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#define SPARE_A1 (REGISTERS_BASE + 0x0994)
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#define SPARE_A2 (REGISTERS_BASE + 0x0998)
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#define SPARE_A3 (REGISTERS_BASE + 0x099C)
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#define SPARE_A4 (REGISTERS_BASE + 0x09A0)
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#define SPARE_A5 (REGISTERS_BASE + 0x09A4)
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#define SPARE_A6 (REGISTERS_BASE + 0x09A8)
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#define SPARE_A7 (REGISTERS_BASE + 0x09AC)
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#define SPARE_A8 (REGISTERS_BASE + 0x09B0)
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#define SPARE_B1 (REGISTERS_BASE + 0x5420)
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#define SPARE_B2 (REGISTERS_BASE + 0x5424)
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#define SPARE_B3 (REGISTERS_BASE + 0x5428)
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#define SPARE_B4 (REGISTERS_BASE + 0x542C)
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#define SPARE_B5 (REGISTERS_BASE + 0x5430)
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#define SPARE_B6 (REGISTERS_BASE + 0x5434)
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#define SPARE_B7 (REGISTERS_BASE + 0x5438)
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#define SPARE_B8 (REGISTERS_BASE + 0x543C)
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#define PLL_PARAMETERS (REGISTERS_BASE + 0x6040)
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#define WU_COUNTER_PAUSE (REGISTERS_BASE + 0x6008)
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#define WELP_ARM_COMMAND (REGISTERS_BASE + 0x6100)
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#define DRPW_SCRATCH_START (DRPW_BASE + 0x002C)
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#define ACX_SLV_SOFT_RESET_BIT BIT(1)
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#define ACX_REG_EEPROM_START_BIT BIT(1)
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/* Command/Information Mailbox Pointers */
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/*===============================================
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Command Mailbox Pointer - 32bit RW
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------------------------------------------
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This register holds the start address of
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the command mailbox located in the Wlan hardware memory.
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The host must read this pointer after a reset to
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find the location of the command mailbox.
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The Wlan hardware initializes the command mailbox
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pointer with the default address of the command mailbox.
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The command mailbox pointer is not valid until after
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the host receives the Init Complete interrupt from
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the Wlan hardware.
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===============================================*/
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#define REG_COMMAND_MAILBOX_PTR (SCR_PAD0)
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/*===============================================
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Information Mailbox Pointer - 32bit RW
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------------------------------------------
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This register holds the start address of
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the information mailbox located in the Wlan hardware memory.
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The host must read this pointer after a reset to find
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the location of the information mailbox.
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The Wlan hardware initializes the information mailbox pointer
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with the default address of the information mailbox.
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The information mailbox pointer is not valid
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until after the host receives the Init Complete interrupt from
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the Wlan hardware.
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===============================================*/
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#define REG_EVENT_MAILBOX_PTR (SCR_PAD1)
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/*===============================================
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EEPROM Read/Write Request 32bit RW
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------------------------------------------
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1 EE_READ - EEPROM Read Request 1 - Setting this bit
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loads a single byte of data into the EE_DATA
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register from the EEPROM location specified in
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the EE_ADDR register.
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The Wlan hardware hardware clears this bit automatically.
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EE_DATA is valid when this bit is cleared.
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0 EE_WRITE - EEPROM Write Request - Setting this bit
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writes a single byte of data from the EE_DATA register into the
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EEPROM location specified in the EE_ADDR register.
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The Wlan hardware hardware clears this bit automatically.
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*===============================================*/
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#define ACX_EE_CTL_REG EE_CTL
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#define EE_WRITE 0x00000001ul
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#define EE_READ 0x00000002ul
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/*===============================================
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EEPROM Address - 32bit RW
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------------------------------------------
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This register specifies the address
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within the EEPROM from/to which to read/write data.
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===============================================*/
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#define ACX_EE_ADDR_REG EE_ADDR
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/*===============================================
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EEPROM Data - 32bit RW
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------------------------------------------
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This register either holds the read 8 bits of
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data from the EEPROM or the write data
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to be written to the EEPROM.
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===============================================*/
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#define ACX_EE_DATA_REG EE_DATA
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/*===============================================
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EEPROM Base Address - 32bit RW
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------------------------------------------
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This register holds the upper nine bits
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[23:15] of the 24-bit Wlan hardware memory
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address for burst reads from EEPROM accesses.
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The EEPROM provides the lower 15 bits of this address.
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The MSB of the address from the EEPROM is ignored.
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===============================================*/
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#define ACX_EE_CFG EE_CFG
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/*===============================================
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GPIO Output Values -32bit, RW
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------------------------------------------
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[31:16] Reserved
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[15: 0] Specify the output values (at the output driver inputs) for
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GPIO[15:0], respectively.
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===============================================*/
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#define ACX_GPIO_OUT_REG GPIO_OUT
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#define ACX_MAX_GPIO_LINES 15
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/*===============================================
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Contention window -32bit, RW
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------------------------------------------
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[31:26] Reserved
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[25:16] Max (0x3ff)
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[15:07] Reserved
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[06:00] Current contention window value - default is 0x1F
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===============================================*/
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#define ACX_CONT_WIND_CFG_REG CONT_WIND_CFG
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#define ACX_CONT_WIND_MIN_MASK 0x0000007f
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#define ACX_CONT_WIND_MAX 0x03ff0000
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/*===============================================
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HI_CFG Interface Configuration Register Values
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------------------------------------------
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===============================================*/
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#define HI_CFG_UART_ENABLE 0x00000004
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#define HI_CFG_RST232_ENABLE 0x00000008
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#define HI_CFG_CLOCK_REQ_SELECT 0x00000010
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#define HI_CFG_HOST_INT_ENABLE 0x00000020
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#define HI_CFG_VLYNQ_OUTPUT_ENABLE 0x00000040
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#define HI_CFG_HOST_INT_ACTIVE_LOW 0x00000080
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#define HI_CFG_UART_TX_OUT_GPIO_15 0x00000100
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#define HI_CFG_UART_TX_OUT_GPIO_14 0x00000200
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#define HI_CFG_UART_TX_OUT_GPIO_7 0x00000400
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#define HI_CFG_DEF_VAL \
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(HI_CFG_UART_ENABLE | \
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HI_CFG_RST232_ENABLE | \
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HI_CFG_CLOCK_REQ_SELECT | \
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HI_CFG_HOST_INT_ENABLE)
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#define REF_FREQ_19_2 0
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#define REF_FREQ_26_0 1
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#define REF_FREQ_38_4 2
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#define REF_FREQ_40_0 3
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#define REF_FREQ_33_6 4
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#define REF_FREQ_NUM 5
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#define LUT_PARAM_INTEGER_DIVIDER 0
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#define LUT_PARAM_FRACTIONAL_DIVIDER 1
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#define LUT_PARAM_ATTN_BB 2
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#define LUT_PARAM_ALPHA_BB 3
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#define LUT_PARAM_STOP_TIME_BB 4
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#define LUT_PARAM_BB_PLL_LOOP_FILTER 5
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#define LUT_PARAM_NUM 6
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#define ACX_EEPROMLESS_IND_REG (SCR_PAD4)
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#define USE_EEPROM 0
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#define SOFT_RESET_MAX_TIME 1000000
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#define SOFT_RESET_STALL_TIME 1000
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#define NVS_DATA_BUNDARY_ALIGNMENT 4
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/* Firmware image load chunk size */
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#define CHUNK_SIZE 16384
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/* Firmware image header size */
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#define FW_HDR_SIZE 8
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#define ECPU_CONTROL_HALT 0x00000101
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/******************************************************************************
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CHANNELS, BAND & REG DOMAINS definitions
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******************************************************************************/
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enum {
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RADIO_BAND_2_4GHZ = 0, /* 2.4 Ghz band */
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RADIO_BAND_5GHZ = 1, /* 5 Ghz band */
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RADIO_BAND_JAPAN_4_9_GHZ = 2,
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DEFAULT_BAND = RADIO_BAND_2_4GHZ,
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INVALID_BAND = 0xFE,
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MAX_RADIO_BANDS = 0xFF
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};
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#define SHORT_PREAMBLE_BIT BIT(0) /* CCK or Barker depending on the rate */
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#define OFDM_RATE_BIT BIT(6)
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#define PBCC_RATE_BIT BIT(7)
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enum {
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CCK_LONG = 0,
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CCK_SHORT = SHORT_PREAMBLE_BIT,
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PBCC_LONG = PBCC_RATE_BIT,
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PBCC_SHORT = PBCC_RATE_BIT | SHORT_PREAMBLE_BIT,
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OFDM = OFDM_RATE_BIT
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};
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/******************************************************************************
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Transmit-Descriptor RATE-SET field definitions...
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Define a new "Rate-Set" for TX path that incorporates the
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Rate & Modulation info into a single 16-bit field.
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TxdRateSet_t:
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b15 - Indicates Preamble type (1=SHORT, 0=LONG).
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Notes:
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Must be LONG (0) for 1Mbps rate.
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Does not apply (set to 0) for RevG-OFDM rates.
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b14 - Indicates PBCC encoding (1=PBCC, 0=not).
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Notes:
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Does not apply (set to 0) for rates 1 and 2 Mbps.
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Does not apply (set to 0) for RevG-OFDM rates.
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b13 - Unused (set to 0).
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b12-b0 - Supported Rate indicator bits as defined below.
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******************************************************************************/
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/*************************************************************************
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Interrupt Trigger Register (Host -> WiLink)
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**************************************************************************/
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/* Hardware to Embedded CPU Interrupts - first 32-bit register set */
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/*
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* Host Command Interrupt. Setting this bit masks
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* the interrupt that the host issues to inform
|
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* the FW that it has sent a command
|
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* to the Wlan hardware Command Mailbox.
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*/
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#define INTR_TRIG_CMD BIT(0)
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/*
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* Host Event Acknowlegde Interrupt. The host
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* sets this bit to acknowledge that it received
|
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* the unsolicited information from the event
|
|
* mailbox.
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|
*/
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#define INTR_TRIG_EVENT_ACK BIT(1)
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/*
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* The host sets this bit to inform the Wlan
|
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* FW that a TX packet is in the XFER
|
|
* Buffer #0.
|
|
*/
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#define INTR_TRIG_TX_PROC0 BIT(2)
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|
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/*
|
|
* The host sets this bit to inform the FW
|
|
* that it read a packet from RX XFER
|
|
* Buffer #0.
|
|
*/
|
|
#define INTR_TRIG_RX_PROC0 BIT(3)
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|
|
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#define INTR_TRIG_DEBUG_ACK BIT(4)
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|
|
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#define INTR_TRIG_STATE_CHANGED BIT(5)
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|
|
|
|
|
/* Hardware to Embedded CPU Interrupts - second 32-bit register set */
|
|
|
|
/*
|
|
* The host sets this bit to inform the FW
|
|
* that it read a packet from RX XFER
|
|
* Buffer #1.
|
|
*/
|
|
#define INTR_TRIG_RX_PROC1 BIT(17)
|
|
|
|
/*
|
|
* The host sets this bit to inform the Wlan
|
|
* hardware that a TX packet is in the XFER
|
|
* Buffer #1.
|
|
*/
|
|
#define INTR_TRIG_TX_PROC1 BIT(18)
|
|
|
|
#define WL127X_REG_FUSE_DATA_2_1 0x050a
|
|
#define WL128X_REG_FUSE_DATA_2_1 0x2152
|
|
#define PG_VER_MASK 0x3c
|
|
#define PG_VER_OFFSET 2
|
|
|
|
#define WL127X_PG_MAJOR_VER_MASK 0x3
|
|
#define WL127X_PG_MAJOR_VER_OFFSET 0x0
|
|
#define WL127X_PG_MINOR_VER_MASK 0xc
|
|
#define WL127X_PG_MINOR_VER_OFFSET 0x2
|
|
|
|
#define WL128X_PG_MAJOR_VER_MASK 0xc
|
|
#define WL128X_PG_MAJOR_VER_OFFSET 0x2
|
|
#define WL128X_PG_MINOR_VER_MASK 0x3
|
|
#define WL128X_PG_MINOR_VER_OFFSET 0x0
|
|
|
|
#define WL127X_PG_GET_MAJOR(pg_ver) ((pg_ver & WL127X_PG_MAJOR_VER_MASK) >> \
|
|
WL127X_PG_MAJOR_VER_OFFSET)
|
|
#define WL127X_PG_GET_MINOR(pg_ver) ((pg_ver & WL127X_PG_MINOR_VER_MASK) >> \
|
|
WL127X_PG_MINOR_VER_OFFSET)
|
|
#define WL128X_PG_GET_MAJOR(pg_ver) ((pg_ver & WL128X_PG_MAJOR_VER_MASK) >> \
|
|
WL128X_PG_MAJOR_VER_OFFSET)
|
|
#define WL128X_PG_GET_MINOR(pg_ver) ((pg_ver & WL128X_PG_MINOR_VER_MASK) >> \
|
|
WL128X_PG_MINOR_VER_OFFSET)
|
|
|
|
#define WL12XX_REG_FUSE_BD_ADDR_1 0x00310eb4
|
|
#define WL12XX_REG_FUSE_BD_ADDR_2 0x00310eb8
|
|
|
|
#endif
|