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The Allwinner SoCs have an IP module that handle both the muxing and the GPIOs. This IP has 8 banks of 32 bits, with a number of pins actually useful for each of these banks varying from one to another, and depending on the SoC used on the board. This driver only implements the pinctrl part, the gpio part will come eventually. Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Olof Johansson <olof@lixom.net> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
10 lines
230 B
Plaintext
10 lines
230 B
Plaintext
config ARCH_SUNXI
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bool "Allwinner A1X SOCs" if ARCH_MULTI_V7
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select CLKSRC_MMIO
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select COMMON_CLK
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select GENERIC_CLOCKEVENTS
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select GENERIC_IRQ_CHIP
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select PINCTRL
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select SPARSE_IRQ
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select SUNXI_TIMER
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select PINCTRL_SUNXI |