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If a module is ON then we should read the module parameters from DSP rather than driver cached values Signed-off-by: Omair M Abdullah <omair.m.abdullah@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com> Signed-off-by: Mark Brown <broonie@kernel.org>
350 lines
7.5 KiB
C
350 lines
7.5 KiB
C
/*
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* skl_topology.h - Intel HDA Platform topology header file
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*
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* Copyright (C) 2014-15 Intel Corp
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* Author: Jeeja KP <jeeja.kp@intel.com>
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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*
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*/
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#ifndef __SKL_TOPOLOGY_H__
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#define __SKL_TOPOLOGY_H__
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#include <linux/types.h>
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#include <sound/hdaudio_ext.h>
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#include <sound/soc.h>
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#include "skl.h"
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#include "skl-tplg-interface.h"
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#define BITS_PER_BYTE 8
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#define MAX_TS_GROUPS 8
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#define MAX_DMIC_TS_GROUPS 4
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#define MAX_FIXED_DMIC_PARAMS_SIZE 727
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/* Maximum number of coefficients up down mixer module */
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#define UP_DOWN_MIXER_MAX_COEFF 6
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#define MODULE_MAX_IN_PINS 8
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#define MODULE_MAX_OUT_PINS 8
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enum skl_channel_index {
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SKL_CHANNEL_LEFT = 0,
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SKL_CHANNEL_RIGHT = 1,
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SKL_CHANNEL_CENTER = 2,
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SKL_CHANNEL_LEFT_SURROUND = 3,
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SKL_CHANNEL_CENTER_SURROUND = 3,
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SKL_CHANNEL_RIGHT_SURROUND = 4,
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SKL_CHANNEL_LFE = 7,
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SKL_CHANNEL_INVALID = 0xF,
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};
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enum skl_bitdepth {
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SKL_DEPTH_8BIT = 8,
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SKL_DEPTH_16BIT = 16,
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SKL_DEPTH_24BIT = 24,
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SKL_DEPTH_32BIT = 32,
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SKL_DEPTH_INVALID
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};
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enum skl_s_freq {
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SKL_FS_8000 = 8000,
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SKL_FS_11025 = 11025,
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SKL_FS_12000 = 12000,
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SKL_FS_16000 = 16000,
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SKL_FS_22050 = 22050,
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SKL_FS_24000 = 24000,
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SKL_FS_32000 = 32000,
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SKL_FS_44100 = 44100,
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SKL_FS_48000 = 48000,
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SKL_FS_64000 = 64000,
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SKL_FS_88200 = 88200,
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SKL_FS_96000 = 96000,
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SKL_FS_128000 = 128000,
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SKL_FS_176400 = 176400,
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SKL_FS_192000 = 192000,
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SKL_FS_INVALID
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};
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enum skl_widget_type {
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SKL_WIDGET_VMIXER = 1,
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SKL_WIDGET_MIXER = 2,
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SKL_WIDGET_PGA = 3,
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SKL_WIDGET_MUX = 4
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};
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struct skl_audio_data_format {
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enum skl_s_freq s_freq;
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enum skl_bitdepth bit_depth;
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u32 channel_map;
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enum skl_ch_cfg ch_cfg;
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enum skl_interleaving interleaving;
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u8 number_of_channels;
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u8 valid_bit_depth;
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u8 sample_type;
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u8 reserved[1];
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} __packed;
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struct skl_base_cfg {
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u32 cps;
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u32 ibs;
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u32 obs;
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u32 is_pages;
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struct skl_audio_data_format audio_fmt;
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};
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struct skl_cpr_gtw_cfg {
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u32 node_id;
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u32 dma_buffer_size;
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u32 config_length;
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/* not mandatory; required only for DMIC/I2S */
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u32 config_data[1];
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} __packed;
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struct skl_cpr_cfg {
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struct skl_base_cfg base_cfg;
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struct skl_audio_data_format out_fmt;
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u32 cpr_feature_mask;
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struct skl_cpr_gtw_cfg gtw_cfg;
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} __packed;
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struct skl_src_module_cfg {
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struct skl_base_cfg base_cfg;
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enum skl_s_freq src_cfg;
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} __packed;
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struct notification_mask {
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u32 notify;
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u32 enable;
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} __packed;
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struct skl_up_down_mixer_cfg {
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struct skl_base_cfg base_cfg;
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enum skl_ch_cfg out_ch_cfg;
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/* This should be set to 1 if user coefficients are required */
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u32 coeff_sel;
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/* Pass the user coeff in this array */
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s32 coeff[UP_DOWN_MIXER_MAX_COEFF];
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} __packed;
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struct skl_algo_cfg {
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struct skl_base_cfg base_cfg;
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char params[0];
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} __packed;
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struct skl_base_outfmt_cfg {
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struct skl_base_cfg base_cfg;
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struct skl_audio_data_format out_fmt;
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} __packed;
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enum skl_dma_type {
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SKL_DMA_HDA_HOST_OUTPUT_CLASS = 0,
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SKL_DMA_HDA_HOST_INPUT_CLASS = 1,
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SKL_DMA_HDA_HOST_INOUT_CLASS = 2,
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SKL_DMA_HDA_LINK_OUTPUT_CLASS = 8,
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SKL_DMA_HDA_LINK_INPUT_CLASS = 9,
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SKL_DMA_HDA_LINK_INOUT_CLASS = 0xA,
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SKL_DMA_DMIC_LINK_INPUT_CLASS = 0xB,
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SKL_DMA_I2S_LINK_OUTPUT_CLASS = 0xC,
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SKL_DMA_I2S_LINK_INPUT_CLASS = 0xD,
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};
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union skl_ssp_dma_node {
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u8 val;
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struct {
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u8 time_slot_index:4;
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u8 i2s_instance:4;
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} dma_node;
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};
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union skl_connector_node_id {
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u32 val;
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struct {
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u32 vindex:8;
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u32 dma_type:4;
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u32 rsvd:20;
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} node;
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};
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struct skl_module_fmt {
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u32 channels;
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u32 s_freq;
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u32 bit_depth;
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u32 valid_bit_depth;
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u32 ch_cfg;
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u32 interleaving_style;
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u32 sample_type;
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u32 ch_map;
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};
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struct skl_module_cfg;
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struct skl_module_inst_id {
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u32 module_id;
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u32 instance_id;
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};
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enum skl_module_pin_state {
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SKL_PIN_UNBIND = 0,
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SKL_PIN_BIND_DONE = 1,
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};
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struct skl_module_pin {
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struct skl_module_inst_id id;
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bool is_dynamic;
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bool in_use;
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enum skl_module_pin_state pin_state;
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struct skl_module_cfg *tgt_mcfg;
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};
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struct skl_specific_cfg {
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u32 set_params;
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u32 param_id;
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u32 caps_size;
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u32 *caps;
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};
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enum skl_pipe_state {
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SKL_PIPE_INVALID = 0,
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SKL_PIPE_CREATED = 1,
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SKL_PIPE_PAUSED = 2,
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SKL_PIPE_STARTED = 3
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};
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struct skl_pipe_module {
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struct snd_soc_dapm_widget *w;
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struct list_head node;
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};
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struct skl_pipe_params {
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u8 host_dma_id;
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u8 link_dma_id;
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u32 ch;
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u32 s_freq;
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u32 s_fmt;
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u8 linktype;
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int stream;
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};
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struct skl_pipe {
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u8 ppl_id;
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u8 pipe_priority;
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u16 conn_type;
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u32 memory_pages;
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struct skl_pipe_params *p_params;
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enum skl_pipe_state state;
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struct list_head w_list;
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};
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enum skl_module_state {
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SKL_MODULE_UNINIT = 0,
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SKL_MODULE_INIT_DONE = 1,
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SKL_MODULE_LOADED = 2,
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SKL_MODULE_UNLOADED = 3,
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SKL_MODULE_BIND_DONE = 4
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};
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struct skl_module_cfg {
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char guid[SKL_UUID_STR_SZ];
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struct skl_module_inst_id id;
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u8 domain;
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bool homogenous_inputs;
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bool homogenous_outputs;
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struct skl_module_fmt in_fmt[MODULE_MAX_IN_PINS];
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struct skl_module_fmt out_fmt[MODULE_MAX_OUT_PINS];
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u8 max_in_queue;
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u8 max_out_queue;
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u8 in_queue_mask;
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u8 out_queue_mask;
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u8 in_queue;
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u8 out_queue;
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u32 mcps;
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u32 ibs;
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u32 obs;
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u8 is_loadable;
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u8 core_id;
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u8 dev_type;
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u8 dma_id;
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u8 time_slot;
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u32 params_fixup;
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u32 converter;
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u32 vbus_id;
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u32 mem_pages;
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struct skl_module_pin *m_in_pin;
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struct skl_module_pin *m_out_pin;
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enum skl_module_type m_type;
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enum skl_hw_conn_type hw_conn_type;
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enum skl_module_state m_state;
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struct skl_pipe *pipe;
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struct skl_specific_cfg formats_config;
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};
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struct skl_algo_data {
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u32 param_id;
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u32 set_params;
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u32 max;
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char *params;
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};
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struct skl_pipeline {
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struct skl_pipe *pipe;
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struct list_head node;
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};
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static inline struct skl *get_skl_ctx(struct device *dev)
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{
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struct hdac_ext_bus *ebus = dev_get_drvdata(dev);
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return ebus_to_skl(ebus);
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}
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int skl_tplg_be_update_params(struct snd_soc_dai *dai,
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struct skl_pipe_params *params);
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void skl_tplg_set_be_dmic_config(struct snd_soc_dai *dai,
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struct skl_pipe_params *params, int stream);
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int skl_tplg_init(struct snd_soc_platform *platform,
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struct hdac_ext_bus *ebus);
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struct skl_module_cfg *skl_tplg_fe_get_cpr_module(
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struct snd_soc_dai *dai, int stream);
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int skl_tplg_update_pipe_params(struct device *dev,
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struct skl_module_cfg *mconfig, struct skl_pipe_params *params);
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int skl_create_pipeline(struct skl_sst *ctx, struct skl_pipe *pipe);
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int skl_run_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
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int skl_pause_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
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int skl_delete_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
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int skl_stop_pipe(struct skl_sst *ctx, struct skl_pipe *pipe);
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int skl_init_module(struct skl_sst *ctx, struct skl_module_cfg *module_config);
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int skl_bind_modules(struct skl_sst *ctx, struct skl_module_cfg
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*src_module, struct skl_module_cfg *dst_module);
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int skl_unbind_modules(struct skl_sst *ctx, struct skl_module_cfg
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*src_module, struct skl_module_cfg *dst_module);
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int skl_set_module_params(struct skl_sst *ctx, u32 *params, int size,
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u32 param_id, struct skl_module_cfg *mcfg);
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int skl_get_module_params(struct skl_sst *ctx, u32 *params, int size,
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u32 param_id, struct skl_module_cfg *mcfg);
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enum skl_bitdepth skl_get_bit_depth(int params);
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#endif
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