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The GPIO block on different QorIQ chips could have registers in different endianess. Define the property to specify which endian is used by the hardware. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Li Yang <leoli@freescale.com> Signed-off-by: Kevin Hilman <khilman@linaro.org>
27 lines
839 B
Plaintext
27 lines
839 B
Plaintext
* Freescale MPC512x/MPC8xxx/Layerscape GPIO controller
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Required properties:
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- compatible : Should be "fsl,<soc>-gpio"
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The following <soc>s are known to be supported:
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mpc5121, mpc5125, mpc8349, mpc8572, mpc8610, pq3, qoriq.
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- reg : Address and length of the register set for the device
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- interrupts : Should be the port interrupt shared by all 32 pins.
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- #gpio-cells : Should be two. The first cell is the pin number and
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the second cell is used to specify the gpio polarity:
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0 = active high
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1 = active low
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Optional properties:
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- little-endian : GPIO registers are used as little endian. If not
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present registers are used as big endian by default.
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Example:
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gpio0: gpio@1100 {
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compatible = "fsl,mpc5125-gpio";
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#gpio-cells = <2>;
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reg = <0x1100 0x080>;
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interrupts = <78 0x8>;
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status = "okay";
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};
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