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8263a67e16
This adds support for extended ASIDs (up to 16-bits) on newer SH-X3 cores that implement the PTAEX register and respective functionality. Presently only the 65nm SH7786 (90nm only supports legacy 8-bit ASIDs). The main change is in how the PTE is written out when loading the entry in to the TLB, as well as in how the TLB entry is selectively flushed. While SH-X2 extended mode splits out the memory-mapped U and I-TLB data arrays for extra bits, extended ASID mode splits out the address arrays. While we don't use the memory-mapped data array access, the address array accesses are necessary for selective TLB flushes, so these are implemented newly and replace the generic SH-4 implementation. With this, TLB flushes in switch_mm() are almost non-existent on newer parts. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
61 lines
1.5 KiB
C
61 lines
1.5 KiB
C
/*
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* include/asm-sh/cpu-sh4/mmu_context.h
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*
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* Copyright (C) 1999 Niibe Yutaka
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_CPU_SH4_MMU_CONTEXT_H
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#define __ASM_CPU_SH4_MMU_CONTEXT_H
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#define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */
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#define MMU_PTEL 0xFF000004 /* Page table entry register LOW */
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#define MMU_TTB 0xFF000008 /* Translation table base register */
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#define MMU_TEA 0xFF00000C /* TLB Exception Address */
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#define MMU_PTEA 0xFF000034 /* PTE assistance register */
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#define MMU_PTEAEX 0xFF00007C /* PTE ASID extension register */
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#define MMUCR 0xFF000010 /* MMU Control Register */
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#define MMU_UTLB_ADDRESS_ARRAY 0xF6000000
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#define MMU_UTLB_ADDRESS_ARRAY2 0xF6800000
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#define MMU_PAGE_ASSOC_BIT 0x80
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#define MMUCR_TI (1<<2)
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#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_SUBTYPE_ST40)
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#define MMUCR_SE (1 << 4)
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#else
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#define MMUCR_SE (0)
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#endif
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#ifdef CONFIG_CPU_HAS_PTEAEX
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#define MMUCR_AEX (1 << 6)
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#else
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#define MMUCR_AEX (0)
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#endif
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#ifdef CONFIG_X2TLB
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#define MMUCR_ME (1 << 7)
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#else
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#define MMUCR_ME (0)
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#endif
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#ifdef CONFIG_SH_STORE_QUEUES
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#define MMUCR_SQMD (1 << 9)
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#else
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#define MMUCR_SQMD (0)
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#endif
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#define MMU_NTLB_ENTRIES 64
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#define MMU_CONTROL_INIT (0x05|MMUCR_SQMD|MMUCR_ME|MMUCR_SE|MMUCR_AEX)
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#define TRA 0xff000020
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#define EXPEVT 0xff000024
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#define INTEVT 0xff000028
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#endif /* __ASM_CPU_SH4_MMU_CONTEXT_H */
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