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538d5b3332
Since IOVA allocation failure is not unusual case we need to flush CPUs' rcache in hope we will succeed in next round. However, it is useful to decide whether we need rcache flush step because of two reasons: - Not scalability. On large system with ~100 CPUs iterating and flushing rcache for each CPU becomes serious bottleneck so we may want to defer it. - free_cpu_cached_iovas() does not care about max PFN we are interested in. Thus we may flush our rcaches and still get no new IOVA like in the commonly used scenario: if (dma_limit > DMA_BIT_MASK(32) && dev_is_pci(dev)) iova = alloc_iova_fast(iovad, iova_len, DMA_BIT_MASK(32) >> shift); if (!iova) iova = alloc_iova_fast(iovad, iova_len, dma_limit >> shift); 1. First alloc_iova_fast() call is limited to DMA_BIT_MASK(32) to get PCI devices a SAC address 2. alloc_iova() fails due to full 32-bit space 3. rcaches contain PFNs out of 32-bit space so free_cpu_cached_iovas() throws entries away for nothing and alloc_iova() fails again 4. Next alloc_iova_fast() call cannot take advantage of rcache since we have just defeated caches. In this case we pick the slowest option to proceed. This patch reworks flushed_rcache local flag to be additional function argument instead and control rcache flush step. Also, it updates all users to do the flush as the last chance. Signed-off-by: Tomasz Nowicki <Tomasz.Nowicki@caviumnetworks.com> Reviewed-by: Robin Murphy <robin.murphy@arm.com> Tested-by: Nate Watterson <nwatters@codeaurora.org> Signed-off-by: Joerg Roedel <jroedel@suse.de>
902 lines
26 KiB
C
902 lines
26 KiB
C
/*
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* A fairly generic DMA-API to IOMMU-API glue layer.
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*
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* Copyright (C) 2014-2015 ARM Ltd.
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*
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* based in part on arch/arm/mm/dma-mapping.c:
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* Copyright (C) 2000-2004 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/device.h>
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#include <linux/dma-iommu.h>
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#include <linux/gfp.h>
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#include <linux/huge_mm.h>
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#include <linux/iommu.h>
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#include <linux/iova.h>
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#include <linux/irq.h>
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#include <linux/mm.h>
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#include <linux/pci.h>
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#include <linux/scatterlist.h>
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#include <linux/vmalloc.h>
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#define IOMMU_MAPPING_ERROR 0
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struct iommu_dma_msi_page {
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struct list_head list;
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dma_addr_t iova;
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phys_addr_t phys;
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};
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enum iommu_dma_cookie_type {
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IOMMU_DMA_IOVA_COOKIE,
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IOMMU_DMA_MSI_COOKIE,
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};
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struct iommu_dma_cookie {
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enum iommu_dma_cookie_type type;
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union {
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/* Full allocator for IOMMU_DMA_IOVA_COOKIE */
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struct iova_domain iovad;
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/* Trivial linear page allocator for IOMMU_DMA_MSI_COOKIE */
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dma_addr_t msi_iova;
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};
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struct list_head msi_page_list;
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spinlock_t msi_lock;
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};
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static inline size_t cookie_msi_granule(struct iommu_dma_cookie *cookie)
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{
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if (cookie->type == IOMMU_DMA_IOVA_COOKIE)
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return cookie->iovad.granule;
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return PAGE_SIZE;
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}
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static struct iommu_dma_cookie *cookie_alloc(enum iommu_dma_cookie_type type)
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{
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struct iommu_dma_cookie *cookie;
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cookie = kzalloc(sizeof(*cookie), GFP_KERNEL);
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if (cookie) {
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spin_lock_init(&cookie->msi_lock);
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INIT_LIST_HEAD(&cookie->msi_page_list);
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cookie->type = type;
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}
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return cookie;
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}
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int iommu_dma_init(void)
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{
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return iova_cache_get();
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}
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/**
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* iommu_get_dma_cookie - Acquire DMA-API resources for a domain
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* @domain: IOMMU domain to prepare for DMA-API usage
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*
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* IOMMU drivers should normally call this from their domain_alloc
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* callback when domain->type == IOMMU_DOMAIN_DMA.
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*/
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int iommu_get_dma_cookie(struct iommu_domain *domain)
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{
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if (domain->iova_cookie)
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return -EEXIST;
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domain->iova_cookie = cookie_alloc(IOMMU_DMA_IOVA_COOKIE);
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if (!domain->iova_cookie)
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return -ENOMEM;
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return 0;
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}
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EXPORT_SYMBOL(iommu_get_dma_cookie);
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/**
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* iommu_get_msi_cookie - Acquire just MSI remapping resources
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* @domain: IOMMU domain to prepare
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* @base: Start address of IOVA region for MSI mappings
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*
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* Users who manage their own IOVA allocation and do not want DMA API support,
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* but would still like to take advantage of automatic MSI remapping, can use
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* this to initialise their own domain appropriately. Users should reserve a
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* contiguous IOVA region, starting at @base, large enough to accommodate the
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* number of PAGE_SIZE mappings necessary to cover every MSI doorbell address
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* used by the devices attached to @domain.
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*/
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int iommu_get_msi_cookie(struct iommu_domain *domain, dma_addr_t base)
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{
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struct iommu_dma_cookie *cookie;
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if (domain->type != IOMMU_DOMAIN_UNMANAGED)
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return -EINVAL;
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if (domain->iova_cookie)
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return -EEXIST;
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cookie = cookie_alloc(IOMMU_DMA_MSI_COOKIE);
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if (!cookie)
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return -ENOMEM;
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cookie->msi_iova = base;
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domain->iova_cookie = cookie;
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return 0;
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}
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EXPORT_SYMBOL(iommu_get_msi_cookie);
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/**
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* iommu_put_dma_cookie - Release a domain's DMA mapping resources
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* @domain: IOMMU domain previously prepared by iommu_get_dma_cookie() or
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* iommu_get_msi_cookie()
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*
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* IOMMU drivers should normally call this from their domain_free callback.
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*/
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void iommu_put_dma_cookie(struct iommu_domain *domain)
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{
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struct iommu_dma_cookie *cookie = domain->iova_cookie;
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struct iommu_dma_msi_page *msi, *tmp;
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if (!cookie)
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return;
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if (cookie->type == IOMMU_DMA_IOVA_COOKIE && cookie->iovad.granule)
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put_iova_domain(&cookie->iovad);
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list_for_each_entry_safe(msi, tmp, &cookie->msi_page_list, list) {
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list_del(&msi->list);
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kfree(msi);
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}
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kfree(cookie);
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domain->iova_cookie = NULL;
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}
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EXPORT_SYMBOL(iommu_put_dma_cookie);
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/**
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* iommu_dma_get_resv_regions - Reserved region driver helper
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* @dev: Device from iommu_get_resv_regions()
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* @list: Reserved region list from iommu_get_resv_regions()
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*
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* IOMMU drivers can use this to implement their .get_resv_regions callback
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* for general non-IOMMU-specific reservations. Currently, this covers host
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* bridge windows for PCI devices.
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*/
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void iommu_dma_get_resv_regions(struct device *dev, struct list_head *list)
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{
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struct pci_host_bridge *bridge;
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struct resource_entry *window;
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if (!dev_is_pci(dev))
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return;
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bridge = pci_find_host_bridge(to_pci_dev(dev)->bus);
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resource_list_for_each_entry(window, &bridge->windows) {
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struct iommu_resv_region *region;
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phys_addr_t start;
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size_t length;
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if (resource_type(window->res) != IORESOURCE_MEM)
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continue;
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start = window->res->start - window->offset;
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length = window->res->end - window->res->start + 1;
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region = iommu_alloc_resv_region(start, length, 0,
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IOMMU_RESV_RESERVED);
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if (!region)
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return;
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list_add_tail(®ion->list, list);
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}
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}
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EXPORT_SYMBOL(iommu_dma_get_resv_regions);
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static int cookie_init_hw_msi_region(struct iommu_dma_cookie *cookie,
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phys_addr_t start, phys_addr_t end)
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{
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struct iova_domain *iovad = &cookie->iovad;
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struct iommu_dma_msi_page *msi_page;
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int i, num_pages;
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start -= iova_offset(iovad, start);
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num_pages = iova_align(iovad, end - start) >> iova_shift(iovad);
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msi_page = kcalloc(num_pages, sizeof(*msi_page), GFP_KERNEL);
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if (!msi_page)
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return -ENOMEM;
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for (i = 0; i < num_pages; i++) {
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msi_page[i].phys = start;
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msi_page[i].iova = start;
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INIT_LIST_HEAD(&msi_page[i].list);
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list_add(&msi_page[i].list, &cookie->msi_page_list);
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start += iovad->granule;
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}
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return 0;
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}
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static int iova_reserve_iommu_regions(struct device *dev,
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struct iommu_domain *domain)
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{
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struct iommu_dma_cookie *cookie = domain->iova_cookie;
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struct iova_domain *iovad = &cookie->iovad;
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struct iommu_resv_region *region;
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LIST_HEAD(resv_regions);
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int ret = 0;
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iommu_get_resv_regions(dev, &resv_regions);
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list_for_each_entry(region, &resv_regions, list) {
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unsigned long lo, hi;
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/* We ARE the software that manages these! */
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if (region->type == IOMMU_RESV_SW_MSI)
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continue;
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lo = iova_pfn(iovad, region->start);
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hi = iova_pfn(iovad, region->start + region->length - 1);
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reserve_iova(iovad, lo, hi);
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if (region->type == IOMMU_RESV_MSI)
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ret = cookie_init_hw_msi_region(cookie, region->start,
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region->start + region->length);
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if (ret)
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break;
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}
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iommu_put_resv_regions(dev, &resv_regions);
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return ret;
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}
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/**
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* iommu_dma_init_domain - Initialise a DMA mapping domain
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* @domain: IOMMU domain previously prepared by iommu_get_dma_cookie()
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* @base: IOVA at which the mappable address space starts
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* @size: Size of IOVA space
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* @dev: Device the domain is being initialised for
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*
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* @base and @size should be exact multiples of IOMMU page granularity to
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* avoid rounding surprises. If necessary, we reserve the page at address 0
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* to ensure it is an invalid IOVA. It is safe to reinitialise a domain, but
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* any change which could make prior IOVAs invalid will fail.
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*/
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int iommu_dma_init_domain(struct iommu_domain *domain, dma_addr_t base,
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u64 size, struct device *dev)
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{
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struct iommu_dma_cookie *cookie = domain->iova_cookie;
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struct iova_domain *iovad = &cookie->iovad;
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unsigned long order, base_pfn, end_pfn;
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if (!cookie || cookie->type != IOMMU_DMA_IOVA_COOKIE)
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return -EINVAL;
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/* Use the smallest supported page size for IOVA granularity */
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order = __ffs(domain->pgsize_bitmap);
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base_pfn = max_t(unsigned long, 1, base >> order);
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end_pfn = (base + size - 1) >> order;
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/* Check the domain allows at least some access to the device... */
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if (domain->geometry.force_aperture) {
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if (base > domain->geometry.aperture_end ||
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base + size <= domain->geometry.aperture_start) {
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pr_warn("specified DMA range outside IOMMU capability\n");
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return -EFAULT;
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}
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/* ...then finally give it a kicking to make sure it fits */
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base_pfn = max_t(unsigned long, base_pfn,
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domain->geometry.aperture_start >> order);
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}
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/* start_pfn is always nonzero for an already-initialised domain */
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if (iovad->start_pfn) {
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if (1UL << order != iovad->granule ||
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base_pfn != iovad->start_pfn) {
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pr_warn("Incompatible range for DMA domain\n");
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return -EFAULT;
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}
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return 0;
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}
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init_iova_domain(iovad, 1UL << order, base_pfn);
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if (!dev)
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return 0;
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return iova_reserve_iommu_regions(dev, domain);
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}
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EXPORT_SYMBOL(iommu_dma_init_domain);
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/**
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* dma_info_to_prot - Translate DMA API directions and attributes to IOMMU API
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* page flags.
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* @dir: Direction of DMA transfer
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* @coherent: Is the DMA master cache-coherent?
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* @attrs: DMA attributes for the mapping
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*
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* Return: corresponding IOMMU API page protection flags
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*/
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int dma_info_to_prot(enum dma_data_direction dir, bool coherent,
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unsigned long attrs)
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{
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int prot = coherent ? IOMMU_CACHE : 0;
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if (attrs & DMA_ATTR_PRIVILEGED)
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prot |= IOMMU_PRIV;
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switch (dir) {
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case DMA_BIDIRECTIONAL:
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return prot | IOMMU_READ | IOMMU_WRITE;
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case DMA_TO_DEVICE:
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return prot | IOMMU_READ;
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case DMA_FROM_DEVICE:
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return prot | IOMMU_WRITE;
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default:
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return 0;
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}
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}
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static dma_addr_t iommu_dma_alloc_iova(struct iommu_domain *domain,
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size_t size, dma_addr_t dma_limit, struct device *dev)
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{
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struct iommu_dma_cookie *cookie = domain->iova_cookie;
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struct iova_domain *iovad = &cookie->iovad;
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unsigned long shift, iova_len, iova = 0;
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if (cookie->type == IOMMU_DMA_MSI_COOKIE) {
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cookie->msi_iova += size;
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return cookie->msi_iova - size;
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}
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shift = iova_shift(iovad);
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iova_len = size >> shift;
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/*
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* Freeing non-power-of-two-sized allocations back into the IOVA caches
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* will come back to bite us badly, so we have to waste a bit of space
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* rounding up anything cacheable to make sure that can't happen. The
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* order of the unadjusted size will still match upon freeing.
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*/
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if (iova_len < (1 << (IOVA_RANGE_CACHE_MAX_SIZE - 1)))
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iova_len = roundup_pow_of_two(iova_len);
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if (domain->geometry.force_aperture)
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dma_limit = min(dma_limit, domain->geometry.aperture_end);
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/* Try to get PCI devices a SAC address */
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if (dma_limit > DMA_BIT_MASK(32) && dev_is_pci(dev))
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iova = alloc_iova_fast(iovad, iova_len,
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DMA_BIT_MASK(32) >> shift, false);
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if (!iova)
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iova = alloc_iova_fast(iovad, iova_len, dma_limit >> shift,
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true);
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return (dma_addr_t)iova << shift;
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}
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static void iommu_dma_free_iova(struct iommu_dma_cookie *cookie,
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dma_addr_t iova, size_t size)
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{
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struct iova_domain *iovad = &cookie->iovad;
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/* The MSI case is only ever cleaning up its most recent allocation */
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if (cookie->type == IOMMU_DMA_MSI_COOKIE)
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cookie->msi_iova -= size;
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else
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free_iova_fast(iovad, iova_pfn(iovad, iova),
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size >> iova_shift(iovad));
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}
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static void __iommu_dma_unmap(struct iommu_domain *domain, dma_addr_t dma_addr,
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size_t size)
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{
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struct iommu_dma_cookie *cookie = domain->iova_cookie;
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struct iova_domain *iovad = &cookie->iovad;
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size_t iova_off = iova_offset(iovad, dma_addr);
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dma_addr -= iova_off;
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size = iova_align(iovad, size + iova_off);
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WARN_ON(iommu_unmap(domain, dma_addr, size) != size);
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iommu_dma_free_iova(cookie, dma_addr, size);
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}
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static void __iommu_dma_free_pages(struct page **pages, int count)
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{
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while (count--)
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__free_page(pages[count]);
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kvfree(pages);
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}
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static struct page **__iommu_dma_alloc_pages(unsigned int count,
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unsigned long order_mask, gfp_t gfp)
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{
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struct page **pages;
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unsigned int i = 0, array_size = count * sizeof(*pages);
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order_mask &= (2U << MAX_ORDER) - 1;
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if (!order_mask)
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return NULL;
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if (array_size <= PAGE_SIZE)
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pages = kzalloc(array_size, GFP_KERNEL);
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else
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pages = vzalloc(array_size);
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if (!pages)
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return NULL;
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/* IOMMU can map any pages, so himem can also be used here */
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gfp |= __GFP_NOWARN | __GFP_HIGHMEM;
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while (count) {
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struct page *page = NULL;
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unsigned int order_size;
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/*
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* Higher-order allocations are a convenience rather
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* than a necessity, hence using __GFP_NORETRY until
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* falling back to minimum-order allocations.
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*/
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for (order_mask &= (2U << __fls(count)) - 1;
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order_mask; order_mask &= ~order_size) {
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unsigned int order = __fls(order_mask);
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order_size = 1U << order;
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page = alloc_pages((order_mask - order_size) ?
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gfp | __GFP_NORETRY : gfp, order);
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if (!page)
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continue;
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if (!order)
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break;
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if (!PageCompound(page)) {
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split_page(page, order);
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break;
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} else if (!split_huge_page(page)) {
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break;
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}
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__free_pages(page, order);
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|
}
|
|
if (!page) {
|
|
__iommu_dma_free_pages(pages, i);
|
|
return NULL;
|
|
}
|
|
count -= order_size;
|
|
while (order_size--)
|
|
pages[i++] = page++;
|
|
}
|
|
return pages;
|
|
}
|
|
|
|
/**
|
|
* iommu_dma_free - Free a buffer allocated by iommu_dma_alloc()
|
|
* @dev: Device which owns this buffer
|
|
* @pages: Array of buffer pages as returned by iommu_dma_alloc()
|
|
* @size: Size of buffer in bytes
|
|
* @handle: DMA address of buffer
|
|
*
|
|
* Frees both the pages associated with the buffer, and the array
|
|
* describing them
|
|
*/
|
|
void iommu_dma_free(struct device *dev, struct page **pages, size_t size,
|
|
dma_addr_t *handle)
|
|
{
|
|
__iommu_dma_unmap(iommu_get_domain_for_dev(dev), *handle, size);
|
|
__iommu_dma_free_pages(pages, PAGE_ALIGN(size) >> PAGE_SHIFT);
|
|
*handle = IOMMU_MAPPING_ERROR;
|
|
}
|
|
|
|
/**
|
|
* iommu_dma_alloc - Allocate and map a buffer contiguous in IOVA space
|
|
* @dev: Device to allocate memory for. Must be a real device
|
|
* attached to an iommu_dma_domain
|
|
* @size: Size of buffer in bytes
|
|
* @gfp: Allocation flags
|
|
* @attrs: DMA attributes for this allocation
|
|
* @prot: IOMMU mapping flags
|
|
* @handle: Out argument for allocated DMA handle
|
|
* @flush_page: Arch callback which must ensure PAGE_SIZE bytes from the
|
|
* given VA/PA are visible to the given non-coherent device.
|
|
*
|
|
* If @size is less than PAGE_SIZE, then a full CPU page will be allocated,
|
|
* but an IOMMU which supports smaller pages might not map the whole thing.
|
|
*
|
|
* Return: Array of struct page pointers describing the buffer,
|
|
* or NULL on failure.
|
|
*/
|
|
struct page **iommu_dma_alloc(struct device *dev, size_t size, gfp_t gfp,
|
|
unsigned long attrs, int prot, dma_addr_t *handle,
|
|
void (*flush_page)(struct device *, const void *, phys_addr_t))
|
|
{
|
|
struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
|
|
struct iommu_dma_cookie *cookie = domain->iova_cookie;
|
|
struct iova_domain *iovad = &cookie->iovad;
|
|
struct page **pages;
|
|
struct sg_table sgt;
|
|
dma_addr_t iova;
|
|
unsigned int count, min_size, alloc_sizes = domain->pgsize_bitmap;
|
|
|
|
*handle = IOMMU_MAPPING_ERROR;
|
|
|
|
min_size = alloc_sizes & -alloc_sizes;
|
|
if (min_size < PAGE_SIZE) {
|
|
min_size = PAGE_SIZE;
|
|
alloc_sizes |= PAGE_SIZE;
|
|
} else {
|
|
size = ALIGN(size, min_size);
|
|
}
|
|
if (attrs & DMA_ATTR_ALLOC_SINGLE_PAGES)
|
|
alloc_sizes = min_size;
|
|
|
|
count = PAGE_ALIGN(size) >> PAGE_SHIFT;
|
|
pages = __iommu_dma_alloc_pages(count, alloc_sizes >> PAGE_SHIFT, gfp);
|
|
if (!pages)
|
|
return NULL;
|
|
|
|
size = iova_align(iovad, size);
|
|
iova = iommu_dma_alloc_iova(domain, size, dev->coherent_dma_mask, dev);
|
|
if (!iova)
|
|
goto out_free_pages;
|
|
|
|
if (sg_alloc_table_from_pages(&sgt, pages, count, 0, size, GFP_KERNEL))
|
|
goto out_free_iova;
|
|
|
|
if (!(prot & IOMMU_CACHE)) {
|
|
struct sg_mapping_iter miter;
|
|
/*
|
|
* The CPU-centric flushing implied by SG_MITER_TO_SG isn't
|
|
* sufficient here, so skip it by using the "wrong" direction.
|
|
*/
|
|
sg_miter_start(&miter, sgt.sgl, sgt.orig_nents, SG_MITER_FROM_SG);
|
|
while (sg_miter_next(&miter))
|
|
flush_page(dev, miter.addr, page_to_phys(miter.page));
|
|
sg_miter_stop(&miter);
|
|
}
|
|
|
|
if (iommu_map_sg(domain, iova, sgt.sgl, sgt.orig_nents, prot)
|
|
< size)
|
|
goto out_free_sg;
|
|
|
|
*handle = iova;
|
|
sg_free_table(&sgt);
|
|
return pages;
|
|
|
|
out_free_sg:
|
|
sg_free_table(&sgt);
|
|
out_free_iova:
|
|
iommu_dma_free_iova(cookie, iova, size);
|
|
out_free_pages:
|
|
__iommu_dma_free_pages(pages, count);
|
|
return NULL;
|
|
}
|
|
|
|
/**
|
|
* iommu_dma_mmap - Map a buffer into provided user VMA
|
|
* @pages: Array representing buffer from iommu_dma_alloc()
|
|
* @size: Size of buffer in bytes
|
|
* @vma: VMA describing requested userspace mapping
|
|
*
|
|
* Maps the pages of the buffer in @pages into @vma. The caller is responsible
|
|
* for verifying the correct size and protection of @vma beforehand.
|
|
*/
|
|
|
|
int iommu_dma_mmap(struct page **pages, size_t size, struct vm_area_struct *vma)
|
|
{
|
|
unsigned long uaddr = vma->vm_start;
|
|
unsigned int i, count = PAGE_ALIGN(size) >> PAGE_SHIFT;
|
|
int ret = -ENXIO;
|
|
|
|
for (i = vma->vm_pgoff; i < count && uaddr < vma->vm_end; i++) {
|
|
ret = vm_insert_page(vma, uaddr, pages[i]);
|
|
if (ret)
|
|
break;
|
|
uaddr += PAGE_SIZE;
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
static dma_addr_t __iommu_dma_map(struct device *dev, phys_addr_t phys,
|
|
size_t size, int prot)
|
|
{
|
|
struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
|
|
struct iommu_dma_cookie *cookie = domain->iova_cookie;
|
|
size_t iova_off = 0;
|
|
dma_addr_t iova;
|
|
|
|
if (cookie->type == IOMMU_DMA_IOVA_COOKIE) {
|
|
iova_off = iova_offset(&cookie->iovad, phys);
|
|
size = iova_align(&cookie->iovad, size + iova_off);
|
|
}
|
|
|
|
iova = iommu_dma_alloc_iova(domain, size, dma_get_mask(dev), dev);
|
|
if (!iova)
|
|
return IOMMU_MAPPING_ERROR;
|
|
|
|
if (iommu_map(domain, iova, phys - iova_off, size, prot)) {
|
|
iommu_dma_free_iova(cookie, iova, size);
|
|
return IOMMU_MAPPING_ERROR;
|
|
}
|
|
return iova + iova_off;
|
|
}
|
|
|
|
dma_addr_t iommu_dma_map_page(struct device *dev, struct page *page,
|
|
unsigned long offset, size_t size, int prot)
|
|
{
|
|
return __iommu_dma_map(dev, page_to_phys(page) + offset, size, prot);
|
|
}
|
|
|
|
void iommu_dma_unmap_page(struct device *dev, dma_addr_t handle, size_t size,
|
|
enum dma_data_direction dir, unsigned long attrs)
|
|
{
|
|
__iommu_dma_unmap(iommu_get_domain_for_dev(dev), handle, size);
|
|
}
|
|
|
|
/*
|
|
* Prepare a successfully-mapped scatterlist to give back to the caller.
|
|
*
|
|
* At this point the segments are already laid out by iommu_dma_map_sg() to
|
|
* avoid individually crossing any boundaries, so we merely need to check a
|
|
* segment's start address to avoid concatenating across one.
|
|
*/
|
|
static int __finalise_sg(struct device *dev, struct scatterlist *sg, int nents,
|
|
dma_addr_t dma_addr)
|
|
{
|
|
struct scatterlist *s, *cur = sg;
|
|
unsigned long seg_mask = dma_get_seg_boundary(dev);
|
|
unsigned int cur_len = 0, max_len = dma_get_max_seg_size(dev);
|
|
int i, count = 0;
|
|
|
|
for_each_sg(sg, s, nents, i) {
|
|
/* Restore this segment's original unaligned fields first */
|
|
unsigned int s_iova_off = sg_dma_address(s);
|
|
unsigned int s_length = sg_dma_len(s);
|
|
unsigned int s_iova_len = s->length;
|
|
|
|
s->offset += s_iova_off;
|
|
s->length = s_length;
|
|
sg_dma_address(s) = IOMMU_MAPPING_ERROR;
|
|
sg_dma_len(s) = 0;
|
|
|
|
/*
|
|
* Now fill in the real DMA data. If...
|
|
* - there is a valid output segment to append to
|
|
* - and this segment starts on an IOVA page boundary
|
|
* - but doesn't fall at a segment boundary
|
|
* - and wouldn't make the resulting output segment too long
|
|
*/
|
|
if (cur_len && !s_iova_off && (dma_addr & seg_mask) &&
|
|
(cur_len + s_length <= max_len)) {
|
|
/* ...then concatenate it with the previous one */
|
|
cur_len += s_length;
|
|
} else {
|
|
/* Otherwise start the next output segment */
|
|
if (i > 0)
|
|
cur = sg_next(cur);
|
|
cur_len = s_length;
|
|
count++;
|
|
|
|
sg_dma_address(cur) = dma_addr + s_iova_off;
|
|
}
|
|
|
|
sg_dma_len(cur) = cur_len;
|
|
dma_addr += s_iova_len;
|
|
|
|
if (s_length + s_iova_off < s_iova_len)
|
|
cur_len = 0;
|
|
}
|
|
return count;
|
|
}
|
|
|
|
/*
|
|
* If mapping failed, then just restore the original list,
|
|
* but making sure the DMA fields are invalidated.
|
|
*/
|
|
static void __invalidate_sg(struct scatterlist *sg, int nents)
|
|
{
|
|
struct scatterlist *s;
|
|
int i;
|
|
|
|
for_each_sg(sg, s, nents, i) {
|
|
if (sg_dma_address(s) != IOMMU_MAPPING_ERROR)
|
|
s->offset += sg_dma_address(s);
|
|
if (sg_dma_len(s))
|
|
s->length = sg_dma_len(s);
|
|
sg_dma_address(s) = IOMMU_MAPPING_ERROR;
|
|
sg_dma_len(s) = 0;
|
|
}
|
|
}
|
|
|
|
/*
|
|
* The DMA API client is passing in a scatterlist which could describe
|
|
* any old buffer layout, but the IOMMU API requires everything to be
|
|
* aligned to IOMMU pages. Hence the need for this complicated bit of
|
|
* impedance-matching, to be able to hand off a suitably-aligned list,
|
|
* but still preserve the original offsets and sizes for the caller.
|
|
*/
|
|
int iommu_dma_map_sg(struct device *dev, struct scatterlist *sg,
|
|
int nents, int prot)
|
|
{
|
|
struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
|
|
struct iommu_dma_cookie *cookie = domain->iova_cookie;
|
|
struct iova_domain *iovad = &cookie->iovad;
|
|
struct scatterlist *s, *prev = NULL;
|
|
dma_addr_t iova;
|
|
size_t iova_len = 0;
|
|
unsigned long mask = dma_get_seg_boundary(dev);
|
|
int i;
|
|
|
|
/*
|
|
* Work out how much IOVA space we need, and align the segments to
|
|
* IOVA granules for the IOMMU driver to handle. With some clever
|
|
* trickery we can modify the list in-place, but reversibly, by
|
|
* stashing the unaligned parts in the as-yet-unused DMA fields.
|
|
*/
|
|
for_each_sg(sg, s, nents, i) {
|
|
size_t s_iova_off = iova_offset(iovad, s->offset);
|
|
size_t s_length = s->length;
|
|
size_t pad_len = (mask - iova_len + 1) & mask;
|
|
|
|
sg_dma_address(s) = s_iova_off;
|
|
sg_dma_len(s) = s_length;
|
|
s->offset -= s_iova_off;
|
|
s_length = iova_align(iovad, s_length + s_iova_off);
|
|
s->length = s_length;
|
|
|
|
/*
|
|
* Due to the alignment of our single IOVA allocation, we can
|
|
* depend on these assumptions about the segment boundary mask:
|
|
* - If mask size >= IOVA size, then the IOVA range cannot
|
|
* possibly fall across a boundary, so we don't care.
|
|
* - If mask size < IOVA size, then the IOVA range must start
|
|
* exactly on a boundary, therefore we can lay things out
|
|
* based purely on segment lengths without needing to know
|
|
* the actual addresses beforehand.
|
|
* - The mask must be a power of 2, so pad_len == 0 if
|
|
* iova_len == 0, thus we cannot dereference prev the first
|
|
* time through here (i.e. before it has a meaningful value).
|
|
*/
|
|
if (pad_len && pad_len < s_length - 1) {
|
|
prev->length += pad_len;
|
|
iova_len += pad_len;
|
|
}
|
|
|
|
iova_len += s_length;
|
|
prev = s;
|
|
}
|
|
|
|
iova = iommu_dma_alloc_iova(domain, iova_len, dma_get_mask(dev), dev);
|
|
if (!iova)
|
|
goto out_restore_sg;
|
|
|
|
/*
|
|
* We'll leave any physical concatenation to the IOMMU driver's
|
|
* implementation - it knows better than we do.
|
|
*/
|
|
if (iommu_map_sg(domain, iova, sg, nents, prot) < iova_len)
|
|
goto out_free_iova;
|
|
|
|
return __finalise_sg(dev, sg, nents, iova);
|
|
|
|
out_free_iova:
|
|
iommu_dma_free_iova(cookie, iova, iova_len);
|
|
out_restore_sg:
|
|
__invalidate_sg(sg, nents);
|
|
return 0;
|
|
}
|
|
|
|
void iommu_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
|
|
enum dma_data_direction dir, unsigned long attrs)
|
|
{
|
|
dma_addr_t start, end;
|
|
struct scatterlist *tmp;
|
|
int i;
|
|
/*
|
|
* The scatterlist segments are mapped into a single
|
|
* contiguous IOVA allocation, so this is incredibly easy.
|
|
*/
|
|
start = sg_dma_address(sg);
|
|
for_each_sg(sg_next(sg), tmp, nents - 1, i) {
|
|
if (sg_dma_len(tmp) == 0)
|
|
break;
|
|
sg = tmp;
|
|
}
|
|
end = sg_dma_address(sg) + sg_dma_len(sg);
|
|
__iommu_dma_unmap(iommu_get_domain_for_dev(dev), start, end - start);
|
|
}
|
|
|
|
dma_addr_t iommu_dma_map_resource(struct device *dev, phys_addr_t phys,
|
|
size_t size, enum dma_data_direction dir, unsigned long attrs)
|
|
{
|
|
return __iommu_dma_map(dev, phys, size,
|
|
dma_info_to_prot(dir, false, attrs) | IOMMU_MMIO);
|
|
}
|
|
|
|
void iommu_dma_unmap_resource(struct device *dev, dma_addr_t handle,
|
|
size_t size, enum dma_data_direction dir, unsigned long attrs)
|
|
{
|
|
__iommu_dma_unmap(iommu_get_domain_for_dev(dev), handle, size);
|
|
}
|
|
|
|
int iommu_dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
|
|
{
|
|
return dma_addr == IOMMU_MAPPING_ERROR;
|
|
}
|
|
|
|
static struct iommu_dma_msi_page *iommu_dma_get_msi_page(struct device *dev,
|
|
phys_addr_t msi_addr, struct iommu_domain *domain)
|
|
{
|
|
struct iommu_dma_cookie *cookie = domain->iova_cookie;
|
|
struct iommu_dma_msi_page *msi_page;
|
|
dma_addr_t iova;
|
|
int prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO;
|
|
size_t size = cookie_msi_granule(cookie);
|
|
|
|
msi_addr &= ~(phys_addr_t)(size - 1);
|
|
list_for_each_entry(msi_page, &cookie->msi_page_list, list)
|
|
if (msi_page->phys == msi_addr)
|
|
return msi_page;
|
|
|
|
msi_page = kzalloc(sizeof(*msi_page), GFP_ATOMIC);
|
|
if (!msi_page)
|
|
return NULL;
|
|
|
|
iova = __iommu_dma_map(dev, msi_addr, size, prot);
|
|
if (iommu_dma_mapping_error(dev, iova))
|
|
goto out_free_page;
|
|
|
|
INIT_LIST_HEAD(&msi_page->list);
|
|
msi_page->phys = msi_addr;
|
|
msi_page->iova = iova;
|
|
list_add(&msi_page->list, &cookie->msi_page_list);
|
|
return msi_page;
|
|
|
|
out_free_page:
|
|
kfree(msi_page);
|
|
return NULL;
|
|
}
|
|
|
|
void iommu_dma_map_msi_msg(int irq, struct msi_msg *msg)
|
|
{
|
|
struct device *dev = msi_desc_to_dev(irq_get_msi_desc(irq));
|
|
struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
|
|
struct iommu_dma_cookie *cookie;
|
|
struct iommu_dma_msi_page *msi_page;
|
|
phys_addr_t msi_addr = (u64)msg->address_hi << 32 | msg->address_lo;
|
|
unsigned long flags;
|
|
|
|
if (!domain || !domain->iova_cookie)
|
|
return;
|
|
|
|
cookie = domain->iova_cookie;
|
|
|
|
/*
|
|
* We disable IRQs to rule out a possible inversion against
|
|
* irq_desc_lock if, say, someone tries to retarget the affinity
|
|
* of an MSI from within an IPI handler.
|
|
*/
|
|
spin_lock_irqsave(&cookie->msi_lock, flags);
|
|
msi_page = iommu_dma_get_msi_page(dev, msi_addr, domain);
|
|
spin_unlock_irqrestore(&cookie->msi_lock, flags);
|
|
|
|
if (WARN_ON(!msi_page)) {
|
|
/*
|
|
* We're called from a void callback, so the best we can do is
|
|
* 'fail' by filling the message with obviously bogus values.
|
|
* Since we got this far due to an IOMMU being present, it's
|
|
* not like the existing address would have worked anyway...
|
|
*/
|
|
msg->address_hi = ~0U;
|
|
msg->address_lo = ~0U;
|
|
msg->data = ~0U;
|
|
} else {
|
|
msg->address_hi = upper_32_bits(msi_page->iova);
|
|
msg->address_lo &= cookie_msi_granule(cookie) - 1;
|
|
msg->address_lo += lower_32_bits(msi_page->iova);
|
|
}
|
|
}
|