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65da0a8e34
As pointed out by Russell King in response to the proposed ARM version of this code, the sequence to switch between the UEFI runtime mapping and current's actual userland mapping (and vice versa) is potentially unsafe, since it leaves a time window between the switch to the new page tables and the TLB flush where speculative accesses may hit on stale global TLB entries. So instead, use non-global mappings, and perform the switch via the ordinary ASID-aware context switch routines. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Acked-by: Will Deacon <will.deacon@arm.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
151 lines
3.9 KiB
C
151 lines
3.9 KiB
C
/*
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* Based on arch/arm/include/asm/mmu_context.h
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*
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* Copyright (C) 1996 Russell King.
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_MMU_CONTEXT_H
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#define __ASM_MMU_CONTEXT_H
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#include <linux/compiler.h>
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#include <linux/sched.h>
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#include <asm/cacheflush.h>
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#include <asm/proc-fns.h>
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#include <asm-generic/mm_hooks.h>
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#include <asm/cputype.h>
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#include <asm/pgtable.h>
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#ifdef CONFIG_PID_IN_CONTEXTIDR
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static inline void contextidr_thread_switch(struct task_struct *next)
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{
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asm(
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" msr contextidr_el1, %0\n"
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" isb"
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:
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: "r" (task_pid_nr(next)));
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}
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#else
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static inline void contextidr_thread_switch(struct task_struct *next)
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{
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}
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#endif
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/*
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* Set TTBR0 to empty_zero_page. No translations will be possible via TTBR0.
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*/
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static inline void cpu_set_reserved_ttbr0(void)
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{
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unsigned long ttbr = page_to_phys(empty_zero_page);
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asm(
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" msr ttbr0_el1, %0 // set TTBR0\n"
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" isb"
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:
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: "r" (ttbr));
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}
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/*
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* TCR.T0SZ value to use when the ID map is active. Usually equals
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* TCR_T0SZ(VA_BITS), unless system RAM is positioned very high in
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* physical memory, in which case it will be smaller.
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*/
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extern u64 idmap_t0sz;
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static inline bool __cpu_uses_extended_idmap(void)
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{
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return (!IS_ENABLED(CONFIG_ARM64_VA_BITS_48) &&
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unlikely(idmap_t0sz != TCR_T0SZ(VA_BITS)));
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}
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/*
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* Set TCR.T0SZ to its default value (based on VA_BITS)
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*/
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static inline void cpu_set_default_tcr_t0sz(void)
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{
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unsigned long tcr;
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if (!__cpu_uses_extended_idmap())
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return;
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asm volatile (
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" mrs %0, tcr_el1 ;"
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" bfi %0, %1, %2, %3 ;"
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" msr tcr_el1, %0 ;"
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" isb"
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: "=&r" (tcr)
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: "r"(TCR_T0SZ(VA_BITS)), "I"(TCR_T0SZ_OFFSET), "I"(TCR_TxSZ_WIDTH));
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}
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/*
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* It would be nice to return ASIDs back to the allocator, but unfortunately
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* that introduces a race with a generation rollover where we could erroneously
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* free an ASID allocated in a future generation. We could workaround this by
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* freeing the ASID from the context of the dying mm (e.g. in arch_exit_mmap),
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* but we'd then need to make sure that we didn't dirty any TLBs afterwards.
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* Setting a reserved TTBR0 or EPD0 would work, but it all gets ugly when you
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* take CPU migration into account.
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*/
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#define destroy_context(mm) do { } while(0)
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void check_and_switch_context(struct mm_struct *mm, unsigned int cpu);
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#define init_new_context(tsk,mm) ({ atomic64_set(&(mm)->context.id, 0); 0; })
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/*
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* This is called when "tsk" is about to enter lazy TLB mode.
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*
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* mm: describes the currently active mm context
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* tsk: task which is entering lazy tlb
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* cpu: cpu number which is entering lazy tlb
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*
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* tsk->mm will be NULL
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*/
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static inline void
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enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
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{
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}
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/*
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* This is the actual mm switch as far as the scheduler
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* is concerned. No registers are touched. We avoid
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* calling the CPU specific function when the mm hasn't
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* actually changed.
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*/
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static inline void
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switch_mm(struct mm_struct *prev, struct mm_struct *next,
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struct task_struct *tsk)
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{
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unsigned int cpu = smp_processor_id();
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if (prev == next)
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return;
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/*
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* init_mm.pgd does not contain any user mappings and it is always
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* active for kernel addresses in TTBR1. Just set the reserved TTBR0.
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*/
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if (next == &init_mm) {
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cpu_set_reserved_ttbr0();
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return;
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}
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check_and_switch_context(next, cpu);
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}
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#define deactivate_mm(tsk,mm) do { } while (0)
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#define activate_mm(prev,next) switch_mm(prev, next, NULL)
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#endif
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