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When using VHE, the host needs to clear HCR_EL2.TGE bit in order to interact with guest TLBs, switching from EL2&0 translation regime to EL1&0. However, some non-maskable asynchronous event could happen while TGE is cleared like SDEI. Because of this address translation operations relying on EL2&0 translation regime could fail (tlb invalidation, userspace access, ...). Fix this by properly setting HCR_EL2.TGE when entering NMI context and clear it if necessary when returning to the interrupted context. Signed-off-by: Julien Thierry <julien.thierry@arm.com> Suggested-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: James Morse <james.morse@arm.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Will Deacon <will.deacon@arm.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: James Morse <james.morse@arm.com> Cc: linux-arch@vger.kernel.org Cc: stable@vger.kernel.org Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
78 lines
2.1 KiB
C
78 lines
2.1 KiB
C
/*
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_HARDIRQ_H
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#define __ASM_HARDIRQ_H
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#include <linux/cache.h>
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#include <linux/percpu.h>
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#include <linux/threads.h>
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#include <asm/barrier.h>
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#include <asm/irq.h>
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#include <asm/kvm_arm.h>
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#include <asm/sysreg.h>
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#define NR_IPI 7
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typedef struct {
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unsigned int __softirq_pending;
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unsigned int ipi_irqs[NR_IPI];
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} ____cacheline_aligned irq_cpustat_t;
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#include <linux/irq_cpustat.h> /* Standard mappings for irq_cpustat_t above */
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#define __inc_irq_stat(cpu, member) __IRQ_STAT(cpu, member)++
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#define __get_irq_stat(cpu, member) __IRQ_STAT(cpu, member)
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u64 smp_irq_stat_cpu(unsigned int cpu);
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#define arch_irq_stat_cpu smp_irq_stat_cpu
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#define __ARCH_IRQ_EXIT_IRQS_DISABLED 1
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struct nmi_ctx {
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u64 hcr;
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};
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DECLARE_PER_CPU(struct nmi_ctx, nmi_contexts);
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#define arch_nmi_enter() \
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do { \
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if (is_kernel_in_hyp_mode()) { \
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struct nmi_ctx *nmi_ctx = this_cpu_ptr(&nmi_contexts); \
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nmi_ctx->hcr = read_sysreg(hcr_el2); \
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if (!(nmi_ctx->hcr & HCR_TGE)) { \
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write_sysreg(nmi_ctx->hcr | HCR_TGE, hcr_el2); \
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isb(); \
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} \
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} \
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} while (0)
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#define arch_nmi_exit() \
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do { \
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if (is_kernel_in_hyp_mode()) { \
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struct nmi_ctx *nmi_ctx = this_cpu_ptr(&nmi_contexts); \
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if (!(nmi_ctx->hcr & HCR_TGE)) \
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write_sysreg(nmi_ctx->hcr, hcr_el2); \
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} \
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} while (0)
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static inline void ack_bad_irq(unsigned int irq)
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{
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extern unsigned long irq_err_count;
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irq_err_count++;
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}
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#endif /* __ASM_HARDIRQ_H */
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