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3780444c4f
With the original EEH implementation, the access to config space of the corresponding PCI device is done by RTAS sensitive function. That depends on pci_dn heavily. That would limit EEH extension to other platforms like powernv because other platforms might have different ways to access PCI config space. The patch splits those functions used to access PCI config space and implement them in platform related EEH component. It would be helpful to support EEH on multiple platforms simutaneously in future. Signed-off-by: Gavin Shan <shangw@linux.vnet.ibm.com> Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
292 lines
8.8 KiB
C
292 lines
8.8 KiB
C
/*
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* Copyright (C) 2001 Dave Engebretsen & Todd Inglett IBM Corporation.
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* Copyright 2001-2012 IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef _POWERPC_EEH_H
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#define _POWERPC_EEH_H
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#ifdef __KERNEL__
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#include <linux/init.h>
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#include <linux/list.h>
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#include <linux/string.h>
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struct pci_dev;
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struct pci_bus;
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struct device_node;
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#ifdef CONFIG_EEH
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/*
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* The struct is used to trace EEH state for the associated
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* PCI device node or PCI device. In future, it might
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* represent PE as well so that the EEH device to form
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* another tree except the currently existing tree of PCI
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* buses and PCI devices
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*/
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#define EEH_MODE_SUPPORTED (1<<0) /* EEH supported on the device */
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#define EEH_MODE_NOCHECK (1<<1) /* EEH check should be skipped */
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#define EEH_MODE_ISOLATED (1<<2) /* The device has been isolated */
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#define EEH_MODE_RECOVERING (1<<3) /* Recovering the device */
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#define EEH_MODE_IRQ_DISABLED (1<<4) /* Interrupt disabled */
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struct eeh_dev {
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int mode; /* EEH mode */
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int class_code; /* Class code of the device */
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int config_addr; /* Config address */
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int pe_config_addr; /* PE config address */
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int check_count; /* Times of ignored error */
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int freeze_count; /* Times of froze up */
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int false_positives; /* Times of reported #ff's */
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u32 config_space[16]; /* Saved PCI config space */
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struct pci_controller *phb; /* Associated PHB */
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struct device_node *dn; /* Associated device node */
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struct pci_dev *pdev; /* Associated PCI device */
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};
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static inline struct device_node *eeh_dev_to_of_node(struct eeh_dev *edev)
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{
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return edev->dn;
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}
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static inline struct pci_dev *eeh_dev_to_pci_dev(struct eeh_dev *edev)
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{
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return edev->pdev;
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}
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/*
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* The struct is used to trace the registered EEH operation
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* callback functions. Actually, those operation callback
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* functions are heavily platform dependent. That means the
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* platform should register its own EEH operation callback
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* functions before any EEH further operations.
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*/
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#define EEH_OPT_DISABLE 0 /* EEH disable */
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#define EEH_OPT_ENABLE 1 /* EEH enable */
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#define EEH_OPT_THAW_MMIO 2 /* MMIO enable */
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#define EEH_OPT_THAW_DMA 3 /* DMA enable */
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#define EEH_STATE_UNAVAILABLE (1 << 0) /* State unavailable */
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#define EEH_STATE_NOT_SUPPORT (1 << 1) /* EEH not supported */
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#define EEH_STATE_RESET_ACTIVE (1 << 2) /* Active reset */
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#define EEH_STATE_MMIO_ACTIVE (1 << 3) /* Active MMIO */
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#define EEH_STATE_DMA_ACTIVE (1 << 4) /* Active DMA */
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#define EEH_STATE_MMIO_ENABLED (1 << 5) /* MMIO enabled */
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#define EEH_STATE_DMA_ENABLED (1 << 6) /* DMA enabled */
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#define EEH_RESET_DEACTIVATE 0 /* Deactivate the PE reset */
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#define EEH_RESET_HOT 1 /* Hot reset */
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#define EEH_RESET_FUNDAMENTAL 3 /* Fundamental reset */
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#define EEH_LOG_TEMP 1 /* EEH temporary error log */
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#define EEH_LOG_PERM 2 /* EEH permanent error log */
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struct eeh_ops {
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char *name;
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int (*init)(void);
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int (*set_option)(struct device_node *dn, int option);
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int (*get_pe_addr)(struct device_node *dn);
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int (*get_state)(struct device_node *dn, int *state);
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int (*reset)(struct device_node *dn, int option);
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int (*wait_state)(struct device_node *dn, int max_wait);
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int (*get_log)(struct device_node *dn, int severity, char *drv_log, unsigned long len);
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int (*configure_bridge)(struct device_node *dn);
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int (*read_config)(struct device_node *dn, int where, int size, u32 *val);
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int (*write_config)(struct device_node *dn, int where, int size, u32 val);
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};
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extern struct eeh_ops *eeh_ops;
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extern int eeh_subsystem_enabled;
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/*
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* Max number of EEH freezes allowed before we consider the device
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* to be permanently disabled.
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*/
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#define EEH_MAX_ALLOWED_FREEZES 5
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void * __devinit eeh_dev_init(struct device_node *dn, void *data);
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void __devinit eeh_dev_phb_init_dynamic(struct pci_controller *phb);
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void __init eeh_dev_phb_init(void);
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void __init eeh_init(void);
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#ifdef CONFIG_PPC_PSERIES
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int __init eeh_pseries_init(void);
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#endif
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int __init eeh_ops_register(struct eeh_ops *ops);
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int __exit eeh_ops_unregister(const char *name);
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unsigned long eeh_check_failure(const volatile void __iomem *token,
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unsigned long val);
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int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev);
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void __init pci_addr_cache_build(void);
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void eeh_add_device_tree_early(struct device_node *);
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void eeh_add_device_tree_late(struct pci_bus *);
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void eeh_remove_bus_device(struct pci_dev *);
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/**
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* EEH_POSSIBLE_ERROR() -- test for possible MMIO failure.
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*
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* If this macro yields TRUE, the caller relays to eeh_check_failure()
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* which does further tests out of line.
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*/
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#define EEH_POSSIBLE_ERROR(val, type) ((val) == (type)~0 && eeh_subsystem_enabled)
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/*
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* Reads from a device which has been isolated by EEH will return
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* all 1s. This macro gives an all-1s value of the given size (in
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* bytes: 1, 2, or 4) for comparing with the result of a read.
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*/
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#define EEH_IO_ERROR_VALUE(size) (~0U >> ((4 - (size)) * 8))
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#else /* !CONFIG_EEH */
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static inline void *eeh_dev_init(struct device_node *dn, void *data)
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{
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return NULL;
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}
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static inline void eeh_dev_phb_init_dynamic(struct pci_controller *phb) { }
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static inline void eeh_dev_phb_init(void) { }
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static inline void eeh_init(void) { }
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#ifdef CONFIG_PPC_PSERIES
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static inline int eeh_pseries_init(void)
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{
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return 0;
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}
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#endif /* CONFIG_PPC_PSERIES */
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static inline unsigned long eeh_check_failure(const volatile void __iomem *token, unsigned long val)
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{
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return val;
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}
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static inline int eeh_dn_check_failure(struct device_node *dn, struct pci_dev *dev)
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{
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return 0;
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}
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static inline void pci_addr_cache_build(void) { }
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static inline void eeh_add_device_tree_early(struct device_node *dn) { }
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static inline void eeh_add_device_tree_late(struct pci_bus *bus) { }
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static inline void eeh_remove_bus_device(struct pci_dev *dev) { }
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#define EEH_POSSIBLE_ERROR(val, type) (0)
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#define EEH_IO_ERROR_VALUE(size) (-1UL)
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#endif /* CONFIG_EEH */
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#ifdef CONFIG_PPC64
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/*
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* MMIO read/write operations with EEH support.
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*/
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static inline u8 eeh_readb(const volatile void __iomem *addr)
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{
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u8 val = in_8(addr);
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if (EEH_POSSIBLE_ERROR(val, u8))
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return eeh_check_failure(addr, val);
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return val;
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}
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static inline u16 eeh_readw(const volatile void __iomem *addr)
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{
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u16 val = in_le16(addr);
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if (EEH_POSSIBLE_ERROR(val, u16))
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return eeh_check_failure(addr, val);
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return val;
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}
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static inline u32 eeh_readl(const volatile void __iomem *addr)
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{
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u32 val = in_le32(addr);
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if (EEH_POSSIBLE_ERROR(val, u32))
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return eeh_check_failure(addr, val);
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return val;
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}
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static inline u64 eeh_readq(const volatile void __iomem *addr)
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{
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u64 val = in_le64(addr);
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if (EEH_POSSIBLE_ERROR(val, u64))
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return eeh_check_failure(addr, val);
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return val;
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}
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static inline u16 eeh_readw_be(const volatile void __iomem *addr)
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{
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u16 val = in_be16(addr);
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if (EEH_POSSIBLE_ERROR(val, u16))
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return eeh_check_failure(addr, val);
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return val;
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}
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static inline u32 eeh_readl_be(const volatile void __iomem *addr)
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{
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u32 val = in_be32(addr);
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if (EEH_POSSIBLE_ERROR(val, u32))
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return eeh_check_failure(addr, val);
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return val;
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}
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static inline u64 eeh_readq_be(const volatile void __iomem *addr)
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{
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u64 val = in_be64(addr);
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if (EEH_POSSIBLE_ERROR(val, u64))
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return eeh_check_failure(addr, val);
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return val;
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}
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static inline void eeh_memcpy_fromio(void *dest, const
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volatile void __iomem *src,
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unsigned long n)
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{
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_memcpy_fromio(dest, src, n);
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/* Look for ffff's here at dest[n]. Assume that at least 4 bytes
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* were copied. Check all four bytes.
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*/
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if (n >= 4 && EEH_POSSIBLE_ERROR(*((u32 *)(dest + n - 4)), u32))
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eeh_check_failure(src, *((u32 *)(dest + n - 4)));
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}
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/* in-string eeh macros */
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static inline void eeh_readsb(const volatile void __iomem *addr, void * buf,
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int ns)
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{
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_insb(addr, buf, ns);
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if (EEH_POSSIBLE_ERROR((*(((u8*)buf)+ns-1)), u8))
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eeh_check_failure(addr, *(u8*)buf);
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}
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static inline void eeh_readsw(const volatile void __iomem *addr, void * buf,
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int ns)
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{
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_insw(addr, buf, ns);
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if (EEH_POSSIBLE_ERROR((*(((u16*)buf)+ns-1)), u16))
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eeh_check_failure(addr, *(u16*)buf);
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}
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static inline void eeh_readsl(const volatile void __iomem *addr, void * buf,
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int nl)
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{
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_insl(addr, buf, nl);
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if (EEH_POSSIBLE_ERROR((*(((u32*)buf)+nl-1)), u32))
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eeh_check_failure(addr, *(u32*)buf);
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}
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#endif /* CONFIG_PPC64 */
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#endif /* __KERNEL__ */
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#endif /* _POWERPC_EEH_H */
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