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ea149b36c7
Allow user programs to write mce records into /dev/mcelog. When they do that a fake machine check is triggered to test the machine check code. This uses the MCE MSR wrappers added earlier. The implementation is straight forward. There is a struct mce record per CPU and the MCE MSR accesses get data from there if there is valid data injected there. This allows to test the machine check code relatively realistically because only the lowest layer of hardware access is intercepted. The test suite and injector are available at git://git.kernel.org/pub/scm/utils/cpu/mce/mce-test.git git://git.kernel.org/pub/scm/utils/cpu/mce/mce-inject.git Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
157 lines
4.7 KiB
C
157 lines
4.7 KiB
C
#ifndef _ASM_X86_MCE_H
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#define _ASM_X86_MCE_H
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#include <linux/types.h>
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#include <asm/ioctls.h>
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/*
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* Machine Check support for x86
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*/
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#define MCG_BANKCNT_MASK 0xff /* Number of Banks */
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#define MCG_CTL_P (1ULL<<8) /* MCG_CAP register available */
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#define MCG_EXT_P (1ULL<<9) /* Extended registers available */
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#define MCG_CMCI_P (1ULL<<10) /* CMCI supported */
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#define MCG_EXT_CNT_MASK 0xff0000 /* Number of Extended registers */
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#define MCG_EXT_CNT_SHIFT 16
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#define MCG_EXT_CNT(c) (((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
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#define MCG_STATUS_RIPV (1ULL<<0) /* restart ip valid */
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#define MCG_STATUS_EIPV (1ULL<<1) /* ip points to correct instruction */
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#define MCG_STATUS_MCIP (1ULL<<2) /* machine check in progress */
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#define MCI_STATUS_VAL (1ULL<<63) /* valid error */
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#define MCI_STATUS_OVER (1ULL<<62) /* previous errors lost */
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#define MCI_STATUS_UC (1ULL<<61) /* uncorrected error */
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#define MCI_STATUS_EN (1ULL<<60) /* error enabled */
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#define MCI_STATUS_MISCV (1ULL<<59) /* misc error reg. valid */
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#define MCI_STATUS_ADDRV (1ULL<<58) /* addr reg. valid */
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#define MCI_STATUS_PCC (1ULL<<57) /* processor context corrupt */
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/* Fields are zero when not available */
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struct mce {
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__u64 status;
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__u64 misc;
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__u64 addr;
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__u64 mcgstatus;
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__u64 ip;
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__u64 tsc; /* cpu time stamp counter */
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__u64 res1; /* for future extension */
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__u64 res2; /* dito. */
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__u8 cs; /* code segment */
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__u8 bank; /* machine check bank */
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__u8 cpu; /* cpu that raised the error */
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__u8 finished; /* entry is valid */
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__u32 pad;
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};
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/*
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* This structure contains all data related to the MCE log. Also
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* carries a signature to make it easier to find from external
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* debugging tools. Each entry is only valid when its finished flag
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* is set.
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*/
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#define MCE_LOG_LEN 32
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struct mce_log {
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char signature[12]; /* "MACHINECHECK" */
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unsigned len; /* = MCE_LOG_LEN */
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unsigned next;
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unsigned flags;
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unsigned pad0;
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struct mce entry[MCE_LOG_LEN];
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};
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#define MCE_OVERFLOW 0 /* bit 0 in flags means overflow */
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#define MCE_LOG_SIGNATURE "MACHINECHECK"
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#define MCE_GET_RECORD_LEN _IOR('M', 1, int)
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#define MCE_GET_LOG_LEN _IOR('M', 2, int)
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#define MCE_GETCLEAR_FLAGS _IOR('M', 3, int)
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/* Software defined banks */
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#define MCE_EXTENDED_BANK 128
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#define MCE_THERMAL_BANK MCE_EXTENDED_BANK + 0
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#define K8_MCE_THRESHOLD_BASE (MCE_EXTENDED_BANK + 1) /* MCE_AMD */
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#define K8_MCE_THRESHOLD_BANK_0 (MCE_THRESHOLD_BASE + 0 * 9)
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#define K8_MCE_THRESHOLD_BANK_1 (MCE_THRESHOLD_BASE + 1 * 9)
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#define K8_MCE_THRESHOLD_BANK_2 (MCE_THRESHOLD_BASE + 2 * 9)
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#define K8_MCE_THRESHOLD_BANK_3 (MCE_THRESHOLD_BASE + 3 * 9)
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#define K8_MCE_THRESHOLD_BANK_4 (MCE_THRESHOLD_BASE + 4 * 9)
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#define K8_MCE_THRESHOLD_BANK_5 (MCE_THRESHOLD_BASE + 5 * 9)
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#define K8_MCE_THRESHOLD_DRAM_ECC (MCE_THRESHOLD_BANK_4 + 0)
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#ifdef __KERNEL__
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extern int mce_disabled;
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#include <asm/atomic.h>
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void mce_setup(struct mce *m);
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void mce_log(struct mce *m);
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DECLARE_PER_CPU(struct sys_device, mce_dev);
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extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
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/*
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* To support more than 128 would need to escape the predefined
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* Linux defined extended banks first.
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*/
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#define MAX_NR_BANKS (MCE_EXTENDED_BANK - 1)
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#ifdef CONFIG_X86_MCE_INTEL
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void mce_intel_feature_init(struct cpuinfo_x86 *c);
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void cmci_clear(void);
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void cmci_reenable(void);
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void cmci_rediscover(int dying);
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void cmci_recheck(void);
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#else
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static inline void mce_intel_feature_init(struct cpuinfo_x86 *c) { }
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static inline void cmci_clear(void) {}
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static inline void cmci_reenable(void) {}
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static inline void cmci_rediscover(int dying) {}
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static inline void cmci_recheck(void) {}
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#endif
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#ifdef CONFIG_X86_MCE_AMD
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void mce_amd_feature_init(struct cpuinfo_x86 *c);
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#else
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static inline void mce_amd_feature_init(struct cpuinfo_x86 *c) { }
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#endif
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extern int mce_available(struct cpuinfo_x86 *c);
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void mce_log_therm_throt_event(__u64 status);
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extern atomic_t mce_entry;
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extern void do_machine_check(struct pt_regs *, long);
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typedef DECLARE_BITMAP(mce_banks_t, MAX_NR_BANKS);
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DECLARE_PER_CPU(mce_banks_t, mce_poll_banks);
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enum mcp_flags {
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MCP_TIMESTAMP = (1 << 0), /* log time stamp */
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MCP_UC = (1 << 1), /* log uncorrected errors */
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MCP_DONTLOG = (1 << 2), /* only clear, don't log */
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};
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extern void machine_check_poll(enum mcp_flags flags, mce_banks_t *b);
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extern int mce_notify_user(void);
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DECLARE_PER_CPU(struct mce, injectm);
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extern struct file_operations mce_chrdev_ops;
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#ifdef CONFIG_X86_MCE
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extern void mcheck_init(struct cpuinfo_x86 *c);
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#else
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#define mcheck_init(c) do { } while (0)
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#endif
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extern void (*mce_threshold_vector)(void);
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#endif /* __KERNEL__ */
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#endif /* _ASM_X86_MCE_H */
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