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Joachim Eastwood reports that commitfbfb872f5f"ARM: 8148/1: flush TLS and thumbee register state during exec" causes a boot-time crash on a Cortex-M4 nommu system: Freeing unused kernel memory: 68K (281e5000 - 281f6000) Unhandled exception: IPSR = 00000005 LR = fffffff1 CPU: 0 PID: 1 Comm: swapper Not tainted 3.17.0-rc6-00313-gd2205fa30aa7 #191 task: 29834000 ti: 29832000 task.ti: 29832000 PC is at flush_thread+0x2e/0x40 LR is at flush_thread+0x21/0x40 pc : [<2800954a>] lr : [<2800953d>] psr: 4100000b sp : 29833d60 ip : 00000000 fp : 00000001 r10: 00003cf8 r9 : 29b1f000 r8 : 00000000 r7 : 29b0bc00 r6 : 29834000 r5 : 29832000 r4 : 29832000 r3 : ffff0ff0 r2 : 29832000 r1 : 00000000 r0 : 282121f0 xPSR: 4100000b CPU: 0 PID: 1 Comm: swapper Not tainted 3.17.0-rc6-00313-gd2205fa30aa7 #191 [<2800afa5>] (unwind_backtrace) from [<2800a327>] (show_stack+0xb/0xc) [<2800a327>] (show_stack) from [<2800a963>] (__invalid_entry+0x4b/0x4c) The problem is that set_tls is attempting to clear the TLS location in the kernel-user helper page, which isn't set up on V7M. Fix this by guarding the write to the kuser helper page with a CONFIG_KUSER_HELPERS ifdef. Fixes:fbfb872f5fARM: 8148/1: flush TLS and thumbee register state during exec Reported-by: Joachim Eastwood <manabian@gmail.com> Tested-by: Joachim Eastwood <manabian@gmail.com> Cc: stable@vger.kernel.org Signed-off-by: Nathan Lynch <nathan_lynch@mentor.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
128 lines
3.1 KiB
C
128 lines
3.1 KiB
C
#ifndef __ASMARM_TLS_H
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#define __ASMARM_TLS_H
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#include <linux/compiler.h>
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#include <asm/thread_info.h>
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#ifdef __ASSEMBLY__
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#include <asm/asm-offsets.h>
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.macro switch_tls_none, base, tp, tpuser, tmp1, tmp2
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.endm
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.macro switch_tls_v6k, base, tp, tpuser, tmp1, tmp2
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mrc p15, 0, \tmp2, c13, c0, 2 @ get the user r/w register
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mcr p15, 0, \tp, c13, c0, 3 @ set TLS register
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mcr p15, 0, \tpuser, c13, c0, 2 @ and the user r/w register
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str \tmp2, [\base, #TI_TP_VALUE + 4] @ save it
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.endm
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.macro switch_tls_v6, base, tp, tpuser, tmp1, tmp2
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ldr \tmp1, =elf_hwcap
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ldr \tmp1, [\tmp1, #0]
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mov \tmp2, #0xffff0fff
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tst \tmp1, #HWCAP_TLS @ hardware TLS available?
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streq \tp, [\tmp2, #-15] @ set TLS value at 0xffff0ff0
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mrcne p15, 0, \tmp2, c13, c0, 2 @ get the user r/w register
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mcrne p15, 0, \tp, c13, c0, 3 @ yes, set TLS register
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mcrne p15, 0, \tpuser, c13, c0, 2 @ set user r/w register
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strne \tmp2, [\base, #TI_TP_VALUE + 4] @ save it
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.endm
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.macro switch_tls_software, base, tp, tpuser, tmp1, tmp2
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mov \tmp1, #0xffff0fff
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str \tp, [\tmp1, #-15] @ set TLS value at 0xffff0ff0
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.endm
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#endif
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#ifdef CONFIG_TLS_REG_EMUL
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#define tls_emu 1
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#define has_tls_reg 1
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#define switch_tls switch_tls_none
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#elif defined(CONFIG_CPU_V6)
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#define tls_emu 0
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#define has_tls_reg (elf_hwcap & HWCAP_TLS)
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#define switch_tls switch_tls_v6
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#elif defined(CONFIG_CPU_32v6K)
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#define tls_emu 0
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#define has_tls_reg 1
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#define switch_tls switch_tls_v6k
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#else
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#define tls_emu 0
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#define has_tls_reg 0
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#define switch_tls switch_tls_software
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#endif
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#ifndef __ASSEMBLY__
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static inline void set_tls(unsigned long val)
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{
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struct thread_info *thread;
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thread = current_thread_info();
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thread->tp_value[0] = val;
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/*
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* This code runs with preemption enabled and therefore must
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* be reentrant with respect to switch_tls.
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*
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* We need to ensure ordering between the shadow state and the
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* hardware state, so that we don't corrupt the hardware state
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* with a stale shadow state during context switch.
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*
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* If we're preempted here, switch_tls will load TPIDRURO from
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* thread_info upon resuming execution and the following mcr
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* is merely redundant.
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*/
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barrier();
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if (!tls_emu) {
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if (has_tls_reg) {
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asm("mcr p15, 0, %0, c13, c0, 3"
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: : "r" (val));
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} else {
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#ifdef CONFIG_KUSER_HELPERS
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/*
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* User space must never try to access this
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* directly. Expect your app to break
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* eventually if you do so. The user helper
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* at 0xffff0fe0 must be used instead. (see
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* entry-armv.S for details)
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*/
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*((unsigned int *)0xffff0ff0) = val;
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#endif
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}
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}
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}
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static inline unsigned long get_tpuser(void)
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{
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unsigned long reg = 0;
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if (has_tls_reg && !tls_emu)
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__asm__("mrc p15, 0, %0, c13, c0, 2" : "=r" (reg));
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return reg;
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}
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static inline void set_tpuser(unsigned long val)
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{
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/* Since TPIDRURW is fully context-switched (unlike TPIDRURO),
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* we need not update thread_info.
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*/
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if (has_tls_reg && !tls_emu) {
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asm("mcr p15, 0, %0, c13, c0, 2"
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: : "r" (val));
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}
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}
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static inline void flush_tls(void)
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{
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set_tls(0);
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set_tpuser(0);
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}
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#endif
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#endif /* __ASMARM_TLS_H */
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