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cbda94e039
These changes are mostly for ARM specific device drivers that either don't have an upstream maintainer, or that had the maintainer ask us to pick up the changes to avoid conflicts. A large chunk of this are clock drivers (bcm281xx, exynos, versatile, shmobile), aside from that, reset controllers for STi as well as a large rework of the Marvell Orion/EBU watchdog driver are notable. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIVAwUAUz/1+GCrR//JCVInAQJmfg/9GyqHatDjjUPUBjUQRIEtKgGdmQwdbDqF x+OrS/q5B5zYbpIWkbkt1IUYJfU+89Z5ev9jxI4rV824Nu9Y92mHPDnv+N/ptkIh q2OVP3bQDpWs3aEVV2B1HBNcWrNUuwco9BJu05eegEePii/cto0/wKwWIgUmrmjy xOLthsnp2YmeplGs7ctC6Dz8XbmELebpawejTGylARXei/SwmzB/YYDgJbYjRL2I WSCVa8Vo+MZaGC/yxdKVTtvsKVQenxGoMO3ojikJeRdvuVRJds48Cw+UBdzWYNeJ 3Ssvbdx6Xltf9jy/7H0btOUgxPetZuUV+2XpbWfGu0Zr9FcGDv3q9hrxA+UYKnkY GIGU0otSsmpHnX5Ms3E2xnHiV/fihxA3qohqts5kYRBDr5uc+IpW6SbDymQliCGG OO4XmIVM3pmsqAqP3Zuseemt9CeSW2yC0XlfXkzjO74yY39c+WLBbtGI40Z5W6i0 mM1C8RD3QSNijYCEC8eqz06BQfRImsPs+jllsnJTZaHfbOsib718uvandjfG26lN 616YMcqq0Sp51HIQ4qW7f2dQr7vOyNqbukdkrwF5JgkY/nVki5kdciRg/yeipRy6 Ey80a+OTq0GQljM0F2dcH/A1eHH9KsuI1L6NdSMJsl0h6guIBORPTwTw3qJ13OkR wpJyM+Gm+Fk= =u/FI -----END PGP SIGNATURE----- Merge tag 'drivers-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver changes from Arnd Bergmann: "These changes are mostly for ARM specific device drivers that either don't have an upstream maintainer, or that had the maintainer ask us to pick up the changes to avoid conflicts. A large chunk of this are clock drivers (bcm281xx, exynos, versatile, shmobile), aside from that, reset controllers for STi as well as a large rework of the Marvell Orion/EBU watchdog driver are notable" * tag 'drivers-3.15' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (99 commits) Revert "dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac." Revert "net: stmmac: Add SOCFPGA glue driver" ARM: shmobile: r8a7791: Fix SCIFA3-5 clocks ARM: STi: Add reset controller support to mach-sti Kconfig drivers: reset: stih416: add softreset controller drivers: reset: stih415: add softreset controller drivers: reset: Reset controller driver for STiH416 drivers: reset: Reset controller driver for STiH415 drivers: reset: STi SoC system configuration reset controller support dts: socfpga: Add sysmgr node so the gmac can use to reference dts: socfpga: Add support for SD/MMC on the SOCFPGA platform reset: Add optional resets and stubs ARM: shmobile: r7s72100: fix bus clock calculation Power: Reset: Generalize qnap-poweroff to work on Synology devices. dts: socfpga: Update clock entry to support multiple parents ARM: socfpga: Update socfpga_defconfig dts: socfpga: Add DTS entry for adding the stmmac glue layer for stmmac. net: stmmac: Add SOCFPGA glue driver watchdog: orion_wdt: Use %pa to print 'phys_addr_t' drivers: cci: Export CCI PMU revision ...
87 lines
2.4 KiB
C
87 lines
2.4 KiB
C
/*
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* arch/arm/mach-kirkwood/include/mach/bridge-regs.h
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*
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* Mbus-L to Mbus Bridge Registers
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_BRIDGE_REGS_H
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#define __ASM_ARCH_BRIDGE_REGS_H
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#include <mach/kirkwood.h>
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#define CPU_CONFIG (BRIDGE_VIRT_BASE + 0x0100)
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#define CPU_CONFIG_PHYS (BRIDGE_PHYS_BASE + 0x0100)
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#define CPU_CONFIG_ERROR_PROP 0x00000004
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#define CPU_CONTROL (BRIDGE_VIRT_BASE + 0x0104)
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#define CPU_CONTROL_PHYS (BRIDGE_PHYS_BASE + 0x0104)
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#define CPU_RESET 0x00000002
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#define RSTOUTn_MASK (BRIDGE_VIRT_BASE + 0x0108)
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#define RSTOUTn_MASK_PHYS (BRIDGE_PHYS_BASE + 0x0108)
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#define SOFT_RESET_OUT_EN 0x00000004
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#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE + 0x010c)
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#define SOFT_RESET 0x00000001
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#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE + 0x0110)
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#define BRIDGE_INT_TIMER1_CLR (~0x0004)
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#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0200)
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#define IRQ_CAUSE_LOW_OFF 0x0000
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#define IRQ_MASK_LOW_OFF 0x0004
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#define IRQ_CAUSE_HIGH_OFF 0x0010
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#define IRQ_MASK_HIGH_OFF 0x0014
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#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE + 0x0300)
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#define TIMER_PHYS_BASE (BRIDGE_PHYS_BASE + 0x0300)
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#define L2_CONFIG_REG (BRIDGE_VIRT_BASE + 0x0128)
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#define L2_WRITETHROUGH 0x00000010
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#define CLOCK_GATING_CTRL (BRIDGE_VIRT_BASE + 0x11c)
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#define CGC_BIT_GE0 (0)
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#define CGC_BIT_PEX0 (2)
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#define CGC_BIT_USB0 (3)
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#define CGC_BIT_SDIO (4)
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#define CGC_BIT_TSU (5)
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#define CGC_BIT_DUNIT (6)
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#define CGC_BIT_RUNIT (7)
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#define CGC_BIT_XOR0 (8)
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#define CGC_BIT_AUDIO (9)
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#define CGC_BIT_SATA0 (14)
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#define CGC_BIT_SATA1 (15)
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#define CGC_BIT_XOR1 (16)
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#define CGC_BIT_CRYPTO (17)
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#define CGC_BIT_PEX1 (18)
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#define CGC_BIT_GE1 (19)
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#define CGC_BIT_TDM (20)
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#define CGC_GE0 (1 << 0)
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#define CGC_PEX0 (1 << 2)
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#define CGC_USB0 (1 << 3)
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#define CGC_SDIO (1 << 4)
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#define CGC_TSU (1 << 5)
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#define CGC_DUNIT (1 << 6)
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#define CGC_RUNIT (1 << 7)
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#define CGC_XOR0 (1 << 8)
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#define CGC_AUDIO (1 << 9)
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#define CGC_POWERSAVE (1 << 11)
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#define CGC_SATA0 (1 << 14)
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#define CGC_SATA1 (1 << 15)
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#define CGC_XOR1 (1 << 16)
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#define CGC_CRYPTO (1 << 17)
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#define CGC_PEX1 (1 << 18)
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#define CGC_GE1 (1 << 19)
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#define CGC_TDM (1 << 20)
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#define CGC_RESERVED (0x6 << 21)
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#define MEMORY_PM_CTRL (BRIDGE_VIRT_BASE + 0x118)
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#define MEMORY_PM_CTRL_PHYS (BRIDGE_PHYS_BASE + 0x118)
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#endif
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