mirror of
https://github.com/torvalds/linux.git
synced 2024-12-20 10:01:56 +00:00
e874a66977
This commit implements the base CPU clocks for sunxi devices. It has
been tested using a slightly modified cpufreq driver from the
linux-sunxi 3.0 tree.
Additionally, document the new bindings introduced by this patch.
Idling:
/ # cat /sys/kernel/debug/clk/clk_summary
clock enable_cnt prepare_cnt rate
---------------------------------------------------------------------
osc32k 0 0 32768
osc24M_fixed 0 0 24000000
osc24M 0 0 24000000
apb1_mux 0 0 24000000
apb1 0 0 24000000
pll1 0 0 60000000
cpu 0 0 60000000
axi 0 0 60000000
ahb 0 0 60000000
apb0 0 0 30000000
dummy 0 0 0
After "yes >/dev/null &":
/ # cat /sys/kernel/debug/clk/clk_summary
clock enable_cnt prepare_cnt rate
---------------------------------------------------------------------
osc32k 0 0 32768
osc24M_fixed 0 0 24000000
osc24M 0 0 24000000
apb1_mux 0 0 24000000
apb1 0 0 24000000
pll1 0 0 1008000000
cpu 0 0 1008000000
axi 0 0 336000000
ahb 0 0 168000000
apb0 0 0 84000000
dummy 0 0 0
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
45 lines
1.3 KiB
Plaintext
45 lines
1.3 KiB
Plaintext
Device Tree Clock bindings for arch-sunxi
|
|
|
|
This binding uses the common clock binding[1].
|
|
|
|
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
|
|
|
|
Required properties:
|
|
- compatible : shall be one of the following:
|
|
"allwinner,sunxi-osc-clk" - for a gatable oscillator
|
|
"allwinner,sunxi-pll1-clk" - for the main PLL clock
|
|
"allwinner,sunxi-cpu-clk" - for the CPU multiplexer clock
|
|
"allwinner,sunxi-axi-clk" - for the sunxi AXI clock
|
|
"allwinner,sunxi-ahb-clk" - for the sunxi AHB clock
|
|
"allwinner,sunxi-apb0-clk" - for the sunxi APB0 clock
|
|
"allwinner,sunxi-apb1-clk" - for the sunxi APB1 clock
|
|
"allwinner,sunxi-apb1-mux-clk" - for the sunxi APB1 clock muxing
|
|
|
|
Required properties for all clocks:
|
|
- reg : shall be the control register address for the clock.
|
|
- clocks : shall be the input parent clock(s) phandle for the clock
|
|
- #clock-cells : from common clock binding; shall be set to 0.
|
|
|
|
For example:
|
|
|
|
osc24M: osc24M@01c20050 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sunxi-osc-clk";
|
|
reg = <0x01c20050 0x4>;
|
|
clocks = <&osc24M_fixed>;
|
|
};
|
|
|
|
pll1: pll1@01c20000 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sunxi-pll1-clk";
|
|
reg = <0x01c20000 0x4>;
|
|
clocks = <&osc24M>;
|
|
};
|
|
|
|
cpu: cpu@01c20054 {
|
|
#clock-cells = <0>;
|
|
compatible = "allwinner,sunxi-cpu-clk";
|
|
reg = <0x01c20054 0x4>;
|
|
clocks = <&osc32k>, <&osc24M>, <&pll1>;
|
|
};
|