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The CA9 MPcore SoC Control block is a set of registers that allows to configure certain internal aspects of the core blocks of the SoC (Cortex-A9, L2 cache controller, etc.). In most cases, the default values are fine so they aren't many reasons to touch those registers, but there is one exception: to support cpuidle on Armada 38x, we need to modify the value of the CA9 MPcore Reset Control register. Therefore, this commit adds a new Device Tree binding for this hardware block, and uses this new binding for the Armada 38x Device Tree file. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Cc: devicetree@vger.kernel.org Link: https://lkml.kernel.org/r/1404913221-17343-11-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
15 lines
399 B
Plaintext
15 lines
399 B
Plaintext
Marvell Armada 38x CA9 MPcore SoC Controller
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Required properties:
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- compatible: Should be "marvell,armada-380-mpcore-soc-ctrl".
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- reg: should be the register base and length as documented in the
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datasheet for the CA9 MPcore SoC Control registers
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mpcore-soc-ctrl@20d20 {
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compatible = "marvell,armada-380-mpcore-soc-ctrl";
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reg = <0x20d20 0x6c>;
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};
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