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5257841aaa
PM6125 has the ID 45. Add it. Signed-off-by: Konrad Dybcio <konrad.dybcio@somainline.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20220723100225.92053-2-konrad.dybcio@somainline.org
695 lines
18 KiB
C
695 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2009-2017, The Linux Foundation. All rights reserved.
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* Copyright (c) 2017-2019, Linaro Ltd.
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*/
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#include <linux/debugfs.h>
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/random.h>
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#include <linux/slab.h>
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#include <linux/soc/qcom/smem.h>
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#include <linux/string.h>
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#include <linux/sys_soc.h>
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#include <linux/types.h>
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#include <asm/unaligned.h>
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/*
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* SoC version type with major number in the upper 16 bits and minor
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* number in the lower 16 bits.
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*/
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#define SOCINFO_MAJOR(ver) (((ver) >> 16) & 0xffff)
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#define SOCINFO_MINOR(ver) ((ver) & 0xffff)
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#define SOCINFO_VERSION(maj, min) ((((maj) & 0xffff) << 16)|((min) & 0xffff))
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#define SMEM_SOCINFO_BUILD_ID_LENGTH 32
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#define SMEM_SOCINFO_CHIP_ID_LENGTH 32
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/*
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* SMEM item id, used to acquire handles to respective
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* SMEM region.
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*/
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#define SMEM_HW_SW_BUILD_ID 137
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#ifdef CONFIG_DEBUG_FS
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#define SMEM_IMAGE_VERSION_BLOCKS_COUNT 32
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#define SMEM_IMAGE_VERSION_SIZE 4096
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#define SMEM_IMAGE_VERSION_NAME_SIZE 75
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#define SMEM_IMAGE_VERSION_VARIANT_SIZE 20
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#define SMEM_IMAGE_VERSION_OEM_SIZE 32
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/*
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* SMEM Image table indices
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*/
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#define SMEM_IMAGE_TABLE_BOOT_INDEX 0
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#define SMEM_IMAGE_TABLE_TZ_INDEX 1
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#define SMEM_IMAGE_TABLE_RPM_INDEX 3
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#define SMEM_IMAGE_TABLE_APPS_INDEX 10
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#define SMEM_IMAGE_TABLE_MPSS_INDEX 11
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#define SMEM_IMAGE_TABLE_ADSP_INDEX 12
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#define SMEM_IMAGE_TABLE_CNSS_INDEX 13
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#define SMEM_IMAGE_TABLE_VIDEO_INDEX 14
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#define SMEM_IMAGE_VERSION_TABLE 469
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/*
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* SMEM Image table names
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*/
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static const char *const socinfo_image_names[] = {
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[SMEM_IMAGE_TABLE_ADSP_INDEX] = "adsp",
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[SMEM_IMAGE_TABLE_APPS_INDEX] = "apps",
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[SMEM_IMAGE_TABLE_BOOT_INDEX] = "boot",
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[SMEM_IMAGE_TABLE_CNSS_INDEX] = "cnss",
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[SMEM_IMAGE_TABLE_MPSS_INDEX] = "mpss",
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[SMEM_IMAGE_TABLE_RPM_INDEX] = "rpm",
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[SMEM_IMAGE_TABLE_TZ_INDEX] = "tz",
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[SMEM_IMAGE_TABLE_VIDEO_INDEX] = "video",
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};
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static const char *const pmic_models[] = {
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[0] = "Unknown PMIC model",
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[1] = "PM8941",
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[2] = "PM8841",
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[3] = "PM8019",
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[4] = "PM8226",
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[5] = "PM8110",
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[6] = "PMA8084",
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[7] = "PMI8962",
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[8] = "PMD9635",
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[9] = "PM8994",
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[10] = "PMI8994",
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[11] = "PM8916",
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[12] = "PM8004",
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[13] = "PM8909/PM8058",
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[14] = "PM8028",
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[15] = "PM8901",
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[16] = "PM8950/PM8027",
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[17] = "PMI8950/ISL9519",
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[18] = "PMK8001/PM8921",
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[19] = "PMI8996/PM8018",
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[20] = "PM8998/PM8015",
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[21] = "PMI8998/PM8014",
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[22] = "PM8821",
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[23] = "PM8038",
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[24] = "PM8005/PM8922",
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[25] = "PM8917",
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[26] = "PM660L",
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[27] = "PM660",
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[30] = "PM8150",
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[31] = "PM8150L",
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[32] = "PM8150B",
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[33] = "PMK8002",
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[36] = "PM8009",
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[38] = "PM8150C",
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[41] = "SMB2351",
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[45] = "PM6125",
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[47] = "PMK8350",
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[48] = "PM8350",
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[49] = "PM8350C",
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[50] = "PM8350B",
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[51] = "PMR735A",
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[52] = "PMR735B",
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[58] = "PM8450",
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[65] = "PM8010",
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};
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#endif /* CONFIG_DEBUG_FS */
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/* Socinfo SMEM item structure */
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struct socinfo {
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__le32 fmt;
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__le32 id;
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__le32 ver;
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char build_id[SMEM_SOCINFO_BUILD_ID_LENGTH];
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/* Version 2 */
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__le32 raw_id;
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__le32 raw_ver;
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/* Version 3 */
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__le32 hw_plat;
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/* Version 4 */
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__le32 plat_ver;
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/* Version 5 */
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__le32 accessory_chip;
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/* Version 6 */
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__le32 hw_plat_subtype;
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/* Version 7 */
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__le32 pmic_model;
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__le32 pmic_die_rev;
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/* Version 8 */
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__le32 pmic_model_1;
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__le32 pmic_die_rev_1;
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__le32 pmic_model_2;
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__le32 pmic_die_rev_2;
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/* Version 9 */
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__le32 foundry_id;
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/* Version 10 */
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__le32 serial_num;
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/* Version 11 */
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__le32 num_pmics;
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__le32 pmic_array_offset;
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/* Version 12 */
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__le32 chip_family;
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__le32 raw_device_family;
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__le32 raw_device_num;
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/* Version 13 */
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__le32 nproduct_id;
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char chip_id[SMEM_SOCINFO_CHIP_ID_LENGTH];
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/* Version 14 */
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__le32 num_clusters;
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__le32 ncluster_array_offset;
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__le32 num_defective_parts;
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__le32 ndefective_parts_array_offset;
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/* Version 15 */
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__le32 nmodem_supported;
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};
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#ifdef CONFIG_DEBUG_FS
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struct socinfo_params {
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u32 raw_device_family;
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u32 hw_plat_subtype;
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u32 accessory_chip;
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u32 raw_device_num;
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u32 chip_family;
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u32 foundry_id;
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u32 plat_ver;
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u32 raw_ver;
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u32 hw_plat;
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u32 fmt;
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u32 nproduct_id;
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u32 num_clusters;
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u32 ncluster_array_offset;
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u32 num_defective_parts;
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u32 ndefective_parts_array_offset;
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u32 nmodem_supported;
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};
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struct smem_image_version {
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char name[SMEM_IMAGE_VERSION_NAME_SIZE];
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char variant[SMEM_IMAGE_VERSION_VARIANT_SIZE];
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char pad;
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char oem[SMEM_IMAGE_VERSION_OEM_SIZE];
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};
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#endif /* CONFIG_DEBUG_FS */
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struct qcom_socinfo {
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struct soc_device *soc_dev;
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struct soc_device_attribute attr;
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#ifdef CONFIG_DEBUG_FS
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struct dentry *dbg_root;
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struct socinfo_params info;
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#endif /* CONFIG_DEBUG_FS */
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};
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struct soc_id {
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unsigned int id;
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const char *name;
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};
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static const struct soc_id soc_id[] = {
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{ 87, "MSM8960" },
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{ 109, "APQ8064" },
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{ 122, "MSM8660A" },
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{ 123, "MSM8260A" },
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{ 124, "APQ8060A" },
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{ 126, "MSM8974" },
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{ 130, "MPQ8064" },
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{ 138, "MSM8960AB" },
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{ 139, "APQ8060AB" },
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{ 140, "MSM8260AB" },
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{ 141, "MSM8660AB" },
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{ 145, "MSM8626" },
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{ 147, "MSM8610" },
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{ 153, "APQ8064AB" },
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{ 158, "MSM8226" },
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{ 159, "MSM8526" },
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{ 161, "MSM8110" },
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{ 162, "MSM8210" },
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{ 163, "MSM8810" },
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{ 164, "MSM8212" },
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{ 165, "MSM8612" },
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{ 166, "MSM8112" },
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{ 168, "MSM8225Q" },
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{ 169, "MSM8625Q" },
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{ 170, "MSM8125Q" },
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{ 172, "APQ8064AA" },
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{ 178, "APQ8084" },
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{ 184, "APQ8074" },
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{ 185, "MSM8274" },
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{ 186, "MSM8674" },
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{ 194, "MSM8974PRO-AC" },
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{ 198, "MSM8126" },
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{ 199, "APQ8026" },
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{ 200, "MSM8926" },
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{ 205, "MSM8326" },
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{ 206, "MSM8916" },
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{ 207, "MSM8994" },
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{ 208, "APQ8074PRO-AA" },
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{ 209, "APQ8074PRO-AB" },
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{ 210, "APQ8074PRO-AC" },
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{ 211, "MSM8274PRO-AA" },
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{ 212, "MSM8274PRO-AB" },
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{ 213, "MSM8274PRO-AC" },
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{ 214, "MSM8674PRO-AA" },
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{ 215, "MSM8674PRO-AB" },
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{ 216, "MSM8674PRO-AC" },
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{ 217, "MSM8974PRO-AA" },
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{ 218, "MSM8974PRO-AB" },
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{ 219, "APQ8028" },
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{ 220, "MSM8128" },
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{ 221, "MSM8228" },
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{ 222, "MSM8528" },
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{ 223, "MSM8628" },
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{ 224, "MSM8928" },
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{ 225, "MSM8510" },
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{ 226, "MSM8512" },
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{ 233, "MSM8936" },
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{ 239, "MSM8939" },
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{ 240, "APQ8036" },
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{ 241, "APQ8039" },
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{ 246, "MSM8996" },
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{ 247, "APQ8016" },
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{ 248, "MSM8216" },
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{ 249, "MSM8116" },
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{ 250, "MSM8616" },
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{ 251, "MSM8992" },
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{ 253, "APQ8094" },
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{ 290, "MDM9607" },
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{ 291, "APQ8096" },
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{ 292, "MSM8998" },
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{ 293, "MSM8953" },
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{ 296, "MDM8207" },
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{ 297, "MDM9207" },
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{ 298, "MDM9307" },
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{ 299, "MDM9628" },
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{ 304, "APQ8053" },
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{ 305, "MSM8996SG" },
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{ 310, "MSM8996AU" },
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{ 311, "APQ8096AU" },
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{ 312, "APQ8096SG" },
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{ 317, "SDM660" },
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{ 318, "SDM630" },
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{ 319, "APQ8098" },
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{ 321, "SDM845" },
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{ 322, "MDM9206" },
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{ 323, "IPQ8074" },
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{ 324, "SDA660" },
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{ 325, "SDM658" },
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{ 326, "SDA658" },
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{ 327, "SDA630" },
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{ 338, "SDM450" },
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{ 341, "SDA845" },
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{ 342, "IPQ8072" },
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{ 343, "IPQ8076" },
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{ 344, "IPQ8078" },
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{ 345, "SDM636" },
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{ 346, "SDA636" },
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{ 349, "SDM632" },
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{ 350, "SDA632" },
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{ 351, "SDA450" },
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{ 356, "SM8250" },
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{ 375, "IPQ8070" },
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{ 376, "IPQ8071" },
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{ 389, "IPQ8072A" },
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{ 390, "IPQ8074A" },
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{ 391, "IPQ8076A" },
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{ 392, "IPQ8078A" },
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{ 394, "SM6125" },
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{ 395, "IPQ8070A" },
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{ 396, "IPQ8071A" },
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{ 402, "IPQ6018" },
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{ 403, "IPQ6028" },
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{ 421, "IPQ6000" },
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{ 422, "IPQ6010" },
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{ 425, "SC7180" },
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{ 434, "SM6350" },
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{ 439, "SM8350" },
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{ 449, "SC8280XP" },
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{ 453, "IPQ6005" },
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{ 455, "QRB5165" },
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{ 457, "SM8450" },
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{ 459, "SM7225" },
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{ 460, "SA8295P" },
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{ 461, "SA8540P" },
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{ 480, "SM8450" },
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{ 482, "SM8450" },
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{ 487, "SC7280" },
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{ 495, "SC7180P" },
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{ 507, "SM6375" },
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};
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static const char *socinfo_machine(struct device *dev, unsigned int id)
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{
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int idx;
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for (idx = 0; idx < ARRAY_SIZE(soc_id); idx++) {
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if (soc_id[idx].id == id)
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return soc_id[idx].name;
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}
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return NULL;
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}
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#ifdef CONFIG_DEBUG_FS
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#define QCOM_OPEN(name, _func) \
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static int qcom_open_##name(struct inode *inode, struct file *file) \
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{ \
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return single_open(file, _func, inode->i_private); \
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} \
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\
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static const struct file_operations qcom_ ##name## _ops = { \
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.open = qcom_open_##name, \
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.read = seq_read, \
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.llseek = seq_lseek, \
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.release = single_release, \
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}
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#define DEBUGFS_ADD(info, name) \
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debugfs_create_file(__stringify(name), 0444, \
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qcom_socinfo->dbg_root, \
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info, &qcom_ ##name## _ops)
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static int qcom_show_build_id(struct seq_file *seq, void *p)
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{
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struct socinfo *socinfo = seq->private;
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seq_printf(seq, "%s\n", socinfo->build_id);
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return 0;
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}
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static int qcom_show_pmic_model(struct seq_file *seq, void *p)
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{
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struct socinfo *socinfo = seq->private;
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int model = SOCINFO_MINOR(le32_to_cpu(socinfo->pmic_model));
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if (model < 0)
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return -EINVAL;
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if (model < ARRAY_SIZE(pmic_models) && pmic_models[model])
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seq_printf(seq, "%s\n", pmic_models[model]);
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else
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seq_printf(seq, "unknown (%d)\n", model);
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return 0;
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}
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static int qcom_show_pmic_model_array(struct seq_file *seq, void *p)
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{
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struct socinfo *socinfo = seq->private;
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unsigned int num_pmics = le32_to_cpu(socinfo->num_pmics);
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unsigned int pmic_array_offset = le32_to_cpu(socinfo->pmic_array_offset);
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int i;
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void *ptr = socinfo;
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ptr += pmic_array_offset;
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/* No need for bounds checking, it happened at socinfo_debugfs_init */
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for (i = 0; i < num_pmics; i++) {
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unsigned int model = SOCINFO_MINOR(get_unaligned_le32(ptr + 2 * i * sizeof(u32)));
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unsigned int die_rev = get_unaligned_le32(ptr + (2 * i + 1) * sizeof(u32));
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if (model < ARRAY_SIZE(pmic_models) && pmic_models[model])
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seq_printf(seq, "%s %u.%u\n", pmic_models[model],
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SOCINFO_MAJOR(die_rev),
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SOCINFO_MINOR(die_rev));
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else
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seq_printf(seq, "unknown (%d)\n", model);
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}
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return 0;
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}
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static int qcom_show_pmic_die_revision(struct seq_file *seq, void *p)
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{
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struct socinfo *socinfo = seq->private;
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seq_printf(seq, "%u.%u\n",
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SOCINFO_MAJOR(le32_to_cpu(socinfo->pmic_die_rev)),
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SOCINFO_MINOR(le32_to_cpu(socinfo->pmic_die_rev)));
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return 0;
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}
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static int qcom_show_chip_id(struct seq_file *seq, void *p)
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{
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struct socinfo *socinfo = seq->private;
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seq_printf(seq, "%s\n", socinfo->chip_id);
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return 0;
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}
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QCOM_OPEN(build_id, qcom_show_build_id);
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QCOM_OPEN(pmic_model, qcom_show_pmic_model);
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QCOM_OPEN(pmic_model_array, qcom_show_pmic_model_array);
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QCOM_OPEN(pmic_die_rev, qcom_show_pmic_die_revision);
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QCOM_OPEN(chip_id, qcom_show_chip_id);
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#define DEFINE_IMAGE_OPS(type) \
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static int show_image_##type(struct seq_file *seq, void *p) \
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{ \
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struct smem_image_version *image_version = seq->private; \
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if (image_version->type[0] != '\0') \
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seq_printf(seq, "%s\n", image_version->type); \
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return 0; \
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} \
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static int open_image_##type(struct inode *inode, struct file *file) \
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{ \
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return single_open(file, show_image_##type, inode->i_private); \
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} \
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\
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static const struct file_operations qcom_image_##type##_ops = { \
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.open = open_image_##type, \
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.read = seq_read, \
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.llseek = seq_lseek, \
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.release = single_release, \
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}
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DEFINE_IMAGE_OPS(name);
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DEFINE_IMAGE_OPS(variant);
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DEFINE_IMAGE_OPS(oem);
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static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo,
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struct socinfo *info, size_t info_size)
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|
{
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struct smem_image_version *versions;
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struct dentry *dentry;
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size_t size;
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int i;
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unsigned int num_pmics;
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unsigned int pmic_array_offset;
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|
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qcom_socinfo->dbg_root = debugfs_create_dir("qcom_socinfo", NULL);
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qcom_socinfo->info.fmt = __le32_to_cpu(info->fmt);
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debugfs_create_x32("info_fmt", 0444, qcom_socinfo->dbg_root,
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&qcom_socinfo->info.fmt);
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|
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switch (qcom_socinfo->info.fmt) {
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case SOCINFO_VERSION(0, 15):
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qcom_socinfo->info.nmodem_supported = __le32_to_cpu(info->nmodem_supported);
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debugfs_create_u32("nmodem_supported", 0444, qcom_socinfo->dbg_root,
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&qcom_socinfo->info.nmodem_supported);
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fallthrough;
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case SOCINFO_VERSION(0, 14):
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qcom_socinfo->info.num_clusters = __le32_to_cpu(info->num_clusters);
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qcom_socinfo->info.ncluster_array_offset = __le32_to_cpu(info->ncluster_array_offset);
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qcom_socinfo->info.num_defective_parts = __le32_to_cpu(info->num_defective_parts);
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qcom_socinfo->info.ndefective_parts_array_offset = __le32_to_cpu(info->ndefective_parts_array_offset);
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debugfs_create_u32("num_clusters", 0444, qcom_socinfo->dbg_root,
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&qcom_socinfo->info.num_clusters);
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debugfs_create_u32("ncluster_array_offset", 0444, qcom_socinfo->dbg_root,
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&qcom_socinfo->info.ncluster_array_offset);
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debugfs_create_u32("num_defective_parts", 0444, qcom_socinfo->dbg_root,
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&qcom_socinfo->info.num_defective_parts);
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debugfs_create_u32("ndefective_parts_array_offset", 0444, qcom_socinfo->dbg_root,
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&qcom_socinfo->info.ndefective_parts_array_offset);
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fallthrough;
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case SOCINFO_VERSION(0, 13):
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qcom_socinfo->info.nproduct_id = __le32_to_cpu(info->nproduct_id);
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|
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debugfs_create_u32("nproduct_id", 0444, qcom_socinfo->dbg_root,
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&qcom_socinfo->info.nproduct_id);
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DEBUGFS_ADD(info, chip_id);
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fallthrough;
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case SOCINFO_VERSION(0, 12):
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qcom_socinfo->info.chip_family =
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__le32_to_cpu(info->chip_family);
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qcom_socinfo->info.raw_device_family =
|
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__le32_to_cpu(info->raw_device_family);
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qcom_socinfo->info.raw_device_num =
|
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__le32_to_cpu(info->raw_device_num);
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debugfs_create_x32("chip_family", 0444, qcom_socinfo->dbg_root,
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&qcom_socinfo->info.chip_family);
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debugfs_create_x32("raw_device_family", 0444,
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qcom_socinfo->dbg_root,
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&qcom_socinfo->info.raw_device_family);
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debugfs_create_x32("raw_device_number", 0444,
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qcom_socinfo->dbg_root,
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&qcom_socinfo->info.raw_device_num);
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fallthrough;
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case SOCINFO_VERSION(0, 11):
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num_pmics = le32_to_cpu(info->num_pmics);
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pmic_array_offset = le32_to_cpu(info->pmic_array_offset);
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if (pmic_array_offset + 2 * num_pmics * sizeof(u32) <= info_size)
|
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DEBUGFS_ADD(info, pmic_model_array);
|
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fallthrough;
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case SOCINFO_VERSION(0, 10):
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case SOCINFO_VERSION(0, 9):
|
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qcom_socinfo->info.foundry_id = __le32_to_cpu(info->foundry_id);
|
|
|
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debugfs_create_u32("foundry_id", 0444, qcom_socinfo->dbg_root,
|
|
&qcom_socinfo->info.foundry_id);
|
|
fallthrough;
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case SOCINFO_VERSION(0, 8):
|
|
case SOCINFO_VERSION(0, 7):
|
|
DEBUGFS_ADD(info, pmic_model);
|
|
DEBUGFS_ADD(info, pmic_die_rev);
|
|
fallthrough;
|
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case SOCINFO_VERSION(0, 6):
|
|
qcom_socinfo->info.hw_plat_subtype =
|
|
__le32_to_cpu(info->hw_plat_subtype);
|
|
|
|
debugfs_create_u32("hardware_platform_subtype", 0444,
|
|
qcom_socinfo->dbg_root,
|
|
&qcom_socinfo->info.hw_plat_subtype);
|
|
fallthrough;
|
|
case SOCINFO_VERSION(0, 5):
|
|
qcom_socinfo->info.accessory_chip =
|
|
__le32_to_cpu(info->accessory_chip);
|
|
|
|
debugfs_create_u32("accessory_chip", 0444,
|
|
qcom_socinfo->dbg_root,
|
|
&qcom_socinfo->info.accessory_chip);
|
|
fallthrough;
|
|
case SOCINFO_VERSION(0, 4):
|
|
qcom_socinfo->info.plat_ver = __le32_to_cpu(info->plat_ver);
|
|
|
|
debugfs_create_u32("platform_version", 0444,
|
|
qcom_socinfo->dbg_root,
|
|
&qcom_socinfo->info.plat_ver);
|
|
fallthrough;
|
|
case SOCINFO_VERSION(0, 3):
|
|
qcom_socinfo->info.hw_plat = __le32_to_cpu(info->hw_plat);
|
|
|
|
debugfs_create_u32("hardware_platform", 0444,
|
|
qcom_socinfo->dbg_root,
|
|
&qcom_socinfo->info.hw_plat);
|
|
fallthrough;
|
|
case SOCINFO_VERSION(0, 2):
|
|
qcom_socinfo->info.raw_ver = __le32_to_cpu(info->raw_ver);
|
|
|
|
debugfs_create_u32("raw_version", 0444, qcom_socinfo->dbg_root,
|
|
&qcom_socinfo->info.raw_ver);
|
|
fallthrough;
|
|
case SOCINFO_VERSION(0, 1):
|
|
DEBUGFS_ADD(info, build_id);
|
|
break;
|
|
}
|
|
|
|
versions = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_IMAGE_VERSION_TABLE,
|
|
&size);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(socinfo_image_names); i++) {
|
|
if (!socinfo_image_names[i])
|
|
continue;
|
|
|
|
dentry = debugfs_create_dir(socinfo_image_names[i],
|
|
qcom_socinfo->dbg_root);
|
|
debugfs_create_file("name", 0444, dentry, &versions[i],
|
|
&qcom_image_name_ops);
|
|
debugfs_create_file("variant", 0444, dentry, &versions[i],
|
|
&qcom_image_variant_ops);
|
|
debugfs_create_file("oem", 0444, dentry, &versions[i],
|
|
&qcom_image_oem_ops);
|
|
}
|
|
}
|
|
|
|
static void socinfo_debugfs_exit(struct qcom_socinfo *qcom_socinfo)
|
|
{
|
|
debugfs_remove_recursive(qcom_socinfo->dbg_root);
|
|
}
|
|
#else
|
|
static void socinfo_debugfs_init(struct qcom_socinfo *qcom_socinfo,
|
|
struct socinfo *info, size_t info_size)
|
|
{
|
|
}
|
|
static void socinfo_debugfs_exit(struct qcom_socinfo *qcom_socinfo) { }
|
|
#endif /* CONFIG_DEBUG_FS */
|
|
|
|
static int qcom_socinfo_probe(struct platform_device *pdev)
|
|
{
|
|
struct qcom_socinfo *qs;
|
|
struct socinfo *info;
|
|
size_t item_size;
|
|
|
|
info = qcom_smem_get(QCOM_SMEM_HOST_ANY, SMEM_HW_SW_BUILD_ID,
|
|
&item_size);
|
|
if (IS_ERR(info)) {
|
|
dev_err(&pdev->dev, "Couldn't find socinfo\n");
|
|
return PTR_ERR(info);
|
|
}
|
|
|
|
qs = devm_kzalloc(&pdev->dev, sizeof(*qs), GFP_KERNEL);
|
|
if (!qs)
|
|
return -ENOMEM;
|
|
|
|
qs->attr.family = "Snapdragon";
|
|
qs->attr.machine = socinfo_machine(&pdev->dev,
|
|
le32_to_cpu(info->id));
|
|
qs->attr.soc_id = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%u",
|
|
le32_to_cpu(info->id));
|
|
qs->attr.revision = devm_kasprintf(&pdev->dev, GFP_KERNEL, "%u.%u",
|
|
SOCINFO_MAJOR(le32_to_cpu(info->ver)),
|
|
SOCINFO_MINOR(le32_to_cpu(info->ver)));
|
|
if (offsetof(struct socinfo, serial_num) <= item_size)
|
|
qs->attr.serial_number = devm_kasprintf(&pdev->dev, GFP_KERNEL,
|
|
"%u",
|
|
le32_to_cpu(info->serial_num));
|
|
|
|
qs->soc_dev = soc_device_register(&qs->attr);
|
|
if (IS_ERR(qs->soc_dev))
|
|
return PTR_ERR(qs->soc_dev);
|
|
|
|
socinfo_debugfs_init(qs, info, item_size);
|
|
|
|
/* Feed the soc specific unique data into entropy pool */
|
|
add_device_randomness(info, item_size);
|
|
|
|
platform_set_drvdata(pdev, qs);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int qcom_socinfo_remove(struct platform_device *pdev)
|
|
{
|
|
struct qcom_socinfo *qs = platform_get_drvdata(pdev);
|
|
|
|
soc_device_unregister(qs->soc_dev);
|
|
|
|
socinfo_debugfs_exit(qs);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver qcom_socinfo_driver = {
|
|
.probe = qcom_socinfo_probe,
|
|
.remove = qcom_socinfo_remove,
|
|
.driver = {
|
|
.name = "qcom-socinfo",
|
|
},
|
|
};
|
|
|
|
module_platform_driver(qcom_socinfo_driver);
|
|
|
|
MODULE_DESCRIPTION("Qualcomm SoCinfo driver");
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_ALIAS("platform:qcom-socinfo");
|